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Travelled to:
1 × France
Collaborated with:
E.Beigné A.Valentian B.Giraud O.Thomas T.Benoist Y.Thonnart S.Bernard G.Moritz O.Billoint P.Flatresse J.Noël F.Abouzeid B.Pelloux-Prayer A.Grover S.Clerc P.Roche J.L.Coz S.Engels R.Wilson
Talks about:
silicon (1) voltag (1) design (1) deplet (1) ultra (1) insul (1) fulli (1) wide (1) rang (1) fet (1)

Person: Y. Maneglia

DBLP DBLP: Maneglia:Y=

Contributed to:

DATE 20132013

Wrote 1 papers:

DATE-2013-BeigneVGTBTBMBMFNAPGCRCEW #design
Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs (EB, AV, BG, OT, TB, YT, SB, GM, OB, YM, PF, JPN, FA, BPP, AG, SC, PR, JLC, SE, RW), pp. 613–618.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.