Travelled to:1 × France
Collaborated with:E.Beigné A.Valentian B.Giraud O.Thomas T.Benoist Y.Thonnart S.Bernard G.Moritz O.Billoint P.Flatresse J.Noël F.Abouzeid B.Pelloux-Prayer A.Grover S.Clerc P.Roche J.L.Coz S.Engels R.Wilson
Talks about:silicon (1) voltag (1) design (1) deplet (1) ultra (1) insul (1) fulli (1) wide (1) rang (1) fet (1)
Person: Y. Maneglia
DBLP: Maneglia:Y=
Contributed to:
2013Wrote 1 papers:
- DATE-2013-BeigneVGTBTBMBMFNAPGCRCEW #design
- Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs (EB, AV, BG, OT, TB, YT, SB, GM, OB, YM, PF, JPN, FA, BPP, AG, SC, PR, JLC, SE, RW), pp. 613–618.