Travelled to:2 × France
Collaborated with:B.Lasbouygues N.Azémard P.Maurine E.Beigné A.Valentian B.Giraud O.Thomas T.Benoist Y.Thonnart S.Bernard G.Moritz O.Billoint Y.Maneglia P.Flatresse J.Noël F.Abouzeid B.Pelloux-Prayer A.Grover S.Clerc P.Roche J.L.Coz S.Engels
Talks about:voltag (3) temperatur (1) silicon (1) analysi (1) design (1) deplet (1) applic (1) ultra (1) insul (1) fulli (1)
Person: Robin Wilson
DBLP: Wilson:Robin
Contributed to:
20132007Wrote 2 papers:
- DATE-2013-BeigneVGTBTBMBMFNAPGCRCEW #design
- Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs (EB, AV, BG, OT, TB, YT, SB, GM, OB, YM, PF, JPN, FA, BPP, AG, SC, PR, JLC, SE, RW), pp. 613–618.
- DATE-2007-LasbouyguesWAM #analysis
- Temperature and voltage aware timing analysis: application to voltage drops (BL, RW, NA, PM), pp. 1012–1017.