BibSLEIGH — Martin

Travelled to:

1 × Portugal
4 × Germany
5 × France
7 × USA

Collaborated with:

S.Chakraborty S.Steinhorst M.Glaß J.Teich C.Haubelt S.A.Fahmy M.Kauer F.Sagstetter P.Milbredt P.Mundhenk S.Narayanaswamy F.Reimann D.Goswami S.Shreejith K.Vipin R.Schneider S.Andalam P.Waszecki A.Steininger U.D.Bordoloi M.Streubühr T.Streichert S.Naranayaswami L.Hedrich R.Regler B.Lang H.Stähle A.Knoll A.Masrur S.Ramesh C.Buckl N.Chang S.Park Y.Kim P.Leteinturier H.Adlkofer M.Wolf A.Bouard W.R.Harris S.Jha T.Peyrin A.Poschmann W.Chang

Talks about:

system (10) architectur (9) automot (7) design (7) network (6) softwar (5) analysi (4) vehicl (4) electr (4) optim (4)

Person: Martin Lukasiewycz

DBLP: Lukasiewycz:Martin

Contributed to:

2015

2014

2013

2012

2011

2010

2009

2008

2007

Wrote 27 papers:

DAC-2015-LukasiewyczSS #design #embedded #performance #platform: Efficient design space exploration of embedded platforms (ML, FS, SS), p. 6.
DAC-2015-MundhenkSLFC #analysis #architecture #model checking #probability #security #using: Security analysis of automotive architectures using probabilistic model checking (PM, SS, ML, SAF, SC), p. 6.
DATE-2015-KauerNLSC #geometry #optimisation #programming #using: Inductor optimization for active cell balancing using geometric programming (MK, SN, ML, SS, SC), pp. 281–284.
DATE-2015-MundhenkSLFC #authentication #lightweight #network: Lightweight authentication for secure automotive networks (PM, SS, ML, SAF, SC), pp. 285–288.
DATE-2015-SteinhorstL #composition #identification: Topology identification for smart cells in modular batteries (SS, ML), pp. 1249–1252.
DAC-2014-SagstetterAWLSCK #architecture #framework #integration: Schedule Integration Framework for Time-Triggered Automotive Architectures (FS, SA, PW, ML, HS, SC, AK), p. 6.
DATE-2014-NarayanaswamySLKC #architecture: Optimal dimensioning of active cell balancing architectures (SN, SS, ML, MK, SC), pp. 1–6.
DAC-2013-GoswamiLKSMCR #development #modelling #verification: Model-based development and verification of control software for electric vehicles (DG, ML, MK, SS, AM, SC, SR), p. 9.
DAC-2013-KauerNSLCH #architecture #composition #concurrent: Modular system-level architecture for concurrent cell balancing (MK, SN, SS, ML, SC, LH), p. 10.
DAC-2013-LukasiewyczSASWCKMSFC #architecture #design: System architecture and software design for electric vehicles (ML, SS, SA, FS, PW, WC, MK, PM, SS, SAF, SC), p. 6.
DATE-2013-LukasiewyczSC #programming #using: Priority assignment for event-triggered systems using mathematical programming (ML, SS, SC), pp. 982–987.
DATE-2013-SagstetterLSWBHJPPC #architecture #challenge #design #hardware #security: Security challenges in automotive hardware/software architecture design (FS, ML, SS, MW, AB, WRH, SJ, TP, AP, SC), pp. 458–463.
DATE-2013-ShreejithVFL #approach #configuration management #network #using: An approach for redundancy in FlexRay networks using FPGA partial reconfiguration (SS, KV, SAF, ML), pp. 721–724.
DATE-2012-ChakrabortyLBFCPKLA #challenge #embedded: Embedded systems and software challenges in electric vehicles (SC, ML, CB, SAF, NC, SP, YK, PL, HA), pp. 424–429.
DATE-2012-GoswamiLSC #implementation: Time-triggered implementations of mixed-criticality automotive software (DG, ML, RS, SC), pp. 1227–1232.
DATE-2012-MilbredtGLST #approach #architecture #design: Designing FlexRay-based automotive architectures: A holistic OEM approach (PM, MG, ML, AS, JT), pp. 276–279.
DAC-2011-ReimannLGHT #constraints #realtime #string #synthesis: Symbolic system synthesis in the presence of stringent real-time constraints (FR, ML, MG, CH, JT), pp. 393–398.
DATE-2011-LukasiewyczCM #concept #network #scheduling: FlexRay switch scheduling — A networking concept for electric vehicles (ML, SC, PM), pp. 76–81.
DAC-2010-GlassLHT #analysis #reliability #scalability #towards: Towards scalable system-level reliability analysis (MG, ML, CH, JT), pp. 234–239.
DATE-2010-LukasiewyczGT #design #embedded #robust: Robust design of embedded systems (ML, MG, JT), pp. 1578–1583.
DAC-2009-GlassLTBC #analysis #architecture #design #encoding #hybrid #network: Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis (MG, ML, JT, UDB, SC), pp. 43–46.
DATE-2009-GlassLHT #design #embedded: Incorporating graceful degradation into embedded system design (MG, ML, CH, JT), pp. 320–323.
DATE-2009-LukasiewyczSGHT #architecture #communication #synthesis: Combined system synthesis and communication architecture exploration for MPSoCs (ML, MS, MG, CH, JT), pp. 472–477.
DAC-2008-LukasiewyczGHTRL #concurrent #integration #network #optimisation: Concurrent topology and routing optimization in automotive network integration (ML, MG, CH, JT, RR, BL), pp. 626–629.
DATE-2008-GlassLRHT #analysis #network #optimisation #reliability: Symbolic Reliability Analysis and Optimization of ECU Networks (MG, ML, FR, CH, JT), pp. 158–163.
DATE-2007-GlassLSHT #interactive #synthesis: Interactive presentation: Reliability-aware system synthesis (MG, ML, TS, CH, JT), pp. 409–414.
SAT-2007-LukasiewyczGHT #multi #problem #pseudo: Solving Multi-objective Pseudo-Boolean Problems (ML, MG, CH, JT), pp. 56–69.