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Travelled to:
3 × USA
Collaborated with:
Y.Nitta M.Seki S.Narita K.Uchiyama T.Takahashi R.Satomura E.Haritan H.Yagi P.G.Paulin W.Wolf A.Nohl D.Wingard M.Müller T.Irita M.Ito E.Yamamoto H.Kato G.Sado T.Yamada K.Nishiyama H.Yagi T.Koike Y.Tsuchihashi M.Higashida H.Asano I.Hayashibara K.Tatezawa Y.Shimazaki N.Morino Y.Yasu T.Hoshi Y.Miyairi K.Yanagisawa K.Hirose S.Tamaki S.Yoshioka T.Ishii Y.Kanno H.Mizuno T.Yamada N.Irie R.Tsuchihashi N.Arai T.Akiyama K.Ohno
Talks about:
design (2) power (2) microprocessor (1) superscalar (1) methodolog (1) processor (1) distribut (1) multicor (1) hierarch (1) challeng (1)

Person: Toshihiro Hattori

DBLP DBLP: Hattori:Toshihiro

Contributed to:

DAC 20082008
DAC 20062006
DAC 19981998

Wrote 3 papers:

DAC-2008-HaritanHYPWNWM #challenge #design #exclamation #manycore #question #what
Multicore design is the challenge! what is the solution? (EH, TH, HY, PGP, WW, AN, DW, MM), pp. 128–130.
DAC-2006-HattoriIIYKSYNYKTHAHTSMYHMYHTYIKMYITAAO #mobile #power management
Hierarchical power distribution and power management scheme for a single chip mobile processor (TH, TI, MI, EY, HK, GS, TY, KN, HY, TK, YT, MH, HA, IH, KT, YS, NM, YY, TH, YM, KY, KH, ST, SY, TI, YK, HM, TY, NI, RT, NA, TA, KO), pp. 292–295.
DAC-1998-HattoriNSNUTS #design
Design Methodology of a 200MHz Superscalar Microprocessor: SH-4 (TH, YN, MS, SN, KU, TT, RS), pp. 246–249.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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