Travelled to:1 × France
1 × India
10 × USA
Collaborated with:S.P.Midkiff G.Upadhyaya S.V.Adve H.Kim S.Rixner P.Willmann P.Ranganathan A.Raghunathan Q.Ali D.L.Schuff Y.R.Choe M.Brogioli M.Durbhakula T.Harton V.J.Kozhikkottu A.Pan S.Dey A.Ranjan S.G.Ramasubramanian R.Venkatesan K.Roy
Talks about:network (6) memori (5) interfac (4) programm (3) simul (3) share (3) multiprocessor (2) processor (2) parallel (2) program (2)
Person: Vijay S. Pai
DBLP: Pai:Vijay_S=
Contributed to:
2015
2014
2010
20102007
2005
20042003
2002199919971996Wrote 14 papers:
- DATE-2015-RanjanRVPRR #configuration management #memory management #named #using
- DyReCTape: a dynamically reconfigurable cache using domain wall memory tapes (AR, SGR, RV, VSP, KR, AR), pp. 181–186.
- DAC-2014-KozhikkottuPPDR #clustering #parallel #source code #thread
- Variation Aware Cache Partitioning for Multithreaded Programs (VJK, AP, VSP, SD, AR), p. 6.
- OOPSLA-2010-UpadhyayaMP #automation #identification #memory management #source code
- Automatic atomic region identification in shared memory SPMD programs (GU, SPM, VSP), pp. 652–670.
- PPoPP-2010-AliMP #algorithm #communication #modelling
- Modeling advanced collective communication algorithms on cell-based systems (QA, SPM, VSP), pp. 293–304.
- PPoPP-2010-UpadhyayaMP #data type #generative #performance #using
- Using data structure knowledge for efficient lock generation and strong atomicity (GU, SPM, VSP), pp. 281–292.
- PPoPP-2007-SchuffCP #detection #network #parallel
- Conservative vs. optimistic parallelization of stateful network intrusion detection (DLS, YRC, VSP), pp. 138–139.
- PPoPP-2007-UpadhyayaPM #concurrent
- Expressing and exploiting concurrency in networked applications with aspen (GU, VSP, SPM), pp. 13–23.
- HPCA-2005-WillmannKRP #interface #network #performance #programmable
- An Efficient Programmable 10 Gigabit Ethernet Network Interface Card (PW, HyK, SR, VSP), pp. 96–107.
- LCTES-2004-WillmannBP #architecture #interface #named #network #programmable
- Spinach: a liberty-based simulator for programmable network interface architectures (PW, MB, VSP), pp. 20–29.
- PPoPP-2003-KimPR #concurrent #interface #network #programmable
- Exploiting task-level concurrency in a programmable network interface (HyK, VSP, SR), pp. 61–72.
- ASPLOS-2002-KimPR #interface #network #throughput #web
- Increasing web server throughput with network interface data caching (HyK, VSP, SR), pp. 239–250.
- HPCA-1999-DurbhakulaPA #multi #simulation #trade-off
- Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors (MD, VSP, SVA), pp. 23–32.
- HPCA-1997-PaiRA #parallel #performance #simulation
- The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology (VSP, PR, SVA), pp. 72–83.
- ASPLOS-1996-PaiRAH #consistency #evaluation #memory management #modelling
- An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors (VSP, PR, SVA, TH), pp. 12–23.