Travelled to:
1 × United Kingdom
18 × USA
6 × France
6 × Germany
Collaborated with:
N.K.Jha S.Ravi K.Roy S.Dey S.T.Chakradhar S.Venkataramani K.Lahiri G.Lakshminarayana R.Venkatesan V.J.Kozhikkottu V.K.Chippa J.Coburn T.K.Tan A.Ranjan N.Aaraj K.Sekar A.Muttreja V.Raghunathan A.Raha D.Mohapatra N.R.Potlapally S.G.Ramasubramanian D.Arora M.Sankaradass X.Fong R.B.Lee V.S.Pai M.Zhang C.Li J.Thoguluva M.A.Ghodrat P.Stanley-Marbell I.Ghosh J.Liu M.Shoaib A.A.Goud A.Parandhaman M.Sharad F.Ahmad T.N.Vijaykumar S.Chandra P.Gupta L.Chen D.Bertozzi L.Benini Y.Fei S.Hattangady J.Quisquater W.Wang R.P.Dick M.Lajolo L.Lavagno K.Wakabayashi Y.Kim W.S.Lee A.Pan S.P.Park S.K.Gupta N.N.Mojumder A.Sabne P.C.Kocher G.McGraw K.S.Khouri M.Psarakis D.Gizopoulos M.Hatzimihail A.M.Paschalis
Talks about:
effici (17) design (17) system (16) energi (16) softwar (13) power (12) base (12) architectur (11) embed (10) approxim (9)
Person: Anand Raghunathan
DBLP: Raghunathan:Anand
Contributed to:
Wrote 62 papers:
- DAC-2015-KimLRJR
- Vibration-based secure side channel for medical devices (YK, WSL, VR, NKJ, AR), p. 6.
- DAC-2015-RanjanVFRR #approximate #energy #performance
- Approximate storage for energy efficient spintronic memories (AR, SV, XF, KR, AR), p. 6.
- DAC-2015-VenkataramaniCR #approximate #performance
- Approximate computing and the quest for computing efficiency (SV, STC, KR, AR), p. 6.
- DAC-2015-VenkataramaniRL #classification #energy #machine learning
- Scalable-effort classifiers for energy-efficient machine learning (SV, AR, JL, MS), p. 6.
- DATE-2015-GoudVRR #design #robust #symmetry
- Asymmetric underlapped FinFET based robust SRAM design at 7nm node (AAG, RV, AR, KR), pp. 659–664.
- DATE-2015-RahaVRR #approximate #configuration management #energy #performance #quality
- Quality configurable reduce-and-rank for energy efficient approximate computing (AR, SV, VR, AR), pp. 665–670.
- DATE-2015-RanjanRVPRR #configuration management #memory management #named #using
- DyReCTape: a dynamically reconfigurable cache using domain wall memory tapes (AR, SGR, RV, VSP, KR, AR), pp. 181–186.
- DATE-2015-VenkataramaniCR #approximate
- Computing approximately, and efficiently (SV, STC, KR, AR), pp. 748–751.
- DATE-2015-VenkatesanVFRR #energy #logic #named
- Spintastic: spin-based stochastic logic for energy-efficient computing (RV, SV, XF, KR, AR), pp. 1575–1578.
- DAC-2014-KozhikkottuPPDR #clustering #parallel #source code #thread
- Variation Aware Cache Partitioning for Multithreaded Programs (VJK, AP, VSP, SD, AR), p. 6.
- DATE-2014-RanjanRVRR #approximate #named #synthesis
- ASLAN: Synthesis of approximate sequential circuits (AR, AR, SV, KR, AR), pp. 1–6.
- DAC-2013-ChippaCRR #analysis #approximate
- Analysis and characterization of inherent application resilience for approximate computing (VKC, STC, KR, AR), p. 9.
- DAC-2013-RamasubramanianVPR #design #energy #named
- Relax-and-retime: a methodology for energy-efficient recovery based design (SGR, SV, AP, AR), p. 6.
- DAC-2013-ZhangRJ #network #towards
- Towards trustworthy medical devices and body area networks (MZ, AR, NKJ), p. 6.
- DATE-2013-VenkataramaniRR #approximate #configuration management #design #named #paradigm #quality
- Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits (SV, KR, AR), pp. 1367–1372.
- DATE-2013-VenkatesanSRR #energy #named #performance #using
- DWM-TAPESTRI — an energy efficient all-spin cache using domain wall shift based writes (RV, MS, KR, AR), pp. 1825–1830.
- ASPLOS-2012-AhmadCRV #clustering #named #optimisation #pipes and filters
- Tarazu: optimizing MapReduce on heterogeneous clusters (FA, STC, AR, TNV), pp. 61–74.
- DAC-2012-KozhikkottuDR #design
- Recovery-based design for variation-tolerant SoCs (VJK, SD, AR), pp. 826–833.
- DAC-2012-ParkGMRR #architecture #design #energy #performance #using
- Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture (SPP, SKG, NNM, AR, KR), pp. 492–497.
- DAC-2012-VenkataramaniSKRR #approximate #logic #named #synthesis
- SALSA: systematic logic synthesis of approximate circuits (SV, AS, VJK, KR, AR), pp. 796–801.
- DAC-2011-ChippaRRC #scalability #trade-off
- Dynamic effort scaling: managing the quality-efficiency tradeoff (VKC, AR, KR, STC), pp. 603–608.
- DATE-2011-KozhikkottuVRD #analysis #named #performance #variability
- VESPA: Variability emulation for System-on-Chip performance analysis (VJK, RV, AR, SD), pp. 2–7.
- DATE-2011-MohapatraCRR #approximate #design
- Design of voltage-scalable meta-functions for approximate computing (DM, VKC, AR, KR), pp. 950–955.
- DAC-2010-ChakradharR #hardware #parallel
- Best-effort computing: re-thinking parallel software and hardware (STC, AR), pp. 865–870.
- DAC-2010-ChippaMRRC #algorithm #design #energy #hardware #performance #scalability
- Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency (VKC, DM, AR, KR, STC), pp. 555–560.
- DATE-2009-LiRJ #architecture
- An architecture for secure software defined radio (CL, AR, NKJ), pp. 448–453.
- DATE-2008-ThoguluvaRC #architecture #performance #programmable #security #using
- Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor (JT, AR, STC), pp. 1148–1153.
- DAC-2007-ChandraLRD #power management
- System-on-Chip Power Management Considering Leakage Power Variations (SC, KL, AR, SD), pp. 877–882.
- DAC-2007-GhodratLR #analysis #estimation #hybrid #using
- Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation (MAG, KL, AR), pp. 883–886.
- DATE-2007-AarajRRJ #analysis #energy #execution #framework #platform
- Energy and execution time analysis of a software-based trusted platform module (NA, AR, SR, NKJ), pp. 1128–1133.
- DAC-2006-AroraRRSJC #architecture #mobile #multi #security
- Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC (DA, AR, SR, MS, NKJ, STC), pp. 496–501.
- DAC-2006-PsarakisGHPRR #pipes and filters #self
- Systematic software-based self-test for pipelined processors (MP, DG, MH, AMP, AR, SR), pp. 393–398.
- DATE-2006-SekarLRD #adaptation #configuration management #platform
- Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms (KS, KL, AR, SD), pp. 728–733.
- DATE-2006-Stanley-MarbellLR #adaptation #concurrent #embedded #library #multi #thread
- Adaptive data placement in an embedded multiprocessor thread library (PSM, KL, AR), pp. 698–699.
- DATE-DF-2006-AarajRRJ #architecture #authentication #embedded #performance
- Architectures for efficient face authentication in embedded systems (NA, SR, AR, NKJ), pp. 1–6.
- DATE-DF-2006-PotlapallyRRJL #encryption #framework #satisfiability
- Satisfiability-based framework for enabling side-channel attacks on cryptographic software (NRP, AR, SR, NKJ, RBL), pp. 18–23.
- DAC-2005-CoburnRR #estimation #paradigm
- Power emulation: a new paradigm for power estimation (JC, SR, AR), pp. 700–705.
- DAC-2005-GuptaRRJ #authentication #embedded #performance
- Efficient fingerprint-based user authentication for embedded systems (PG, SR, AR, NKJ), pp. 244–247.
- DAC-2005-MuttrejaRRJ #embedded #energy #estimation #hybrid #simulation
- Hybrid simulation for embedded software energy estimation (AM, AR, SR, NKJ), pp. 23–26.
- DAC-2005-SekarLRD #architecture #communication #configuration management #named
- FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology (KS, KL, AR, SD), pp. 571–574.
- DATE-2005-AroraRRJ #embedded #monitoring #runtime
- Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring (DA, SR, AR, NKJ), pp. 178–183.
- DATE-2005-CoburnRR #estimation #hardware
- Hardware Accelerated Power Estimation (JC, SR, AR), pp. 528–529.
- DAC-2004-MuttrejaRRJ #automation #embedded #energy #megamodelling #performance
- Automated energy/performance macromodeling of embedded software (AM, AR, SR, NKJ), pp. 99–102.
- DAC-2004-RaviKLMR #design #embedded #security
- Security as a new dimension in embedded system design (SR, PCK, RBL, GM, AR), pp. 753–760.
- DAC-2003-ChenRRD #programmable #scalability #self
- A scalable software-based self-test methodology for programmable processors (LC, SR, AR, SD), pp. 548–553.
- DATE-2003-BertozziRBR #embedded #energy #optimisation #performance #protocol
- Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems (DB, AR, LB, SR), pp. 10706–10713.
- DATE-2003-FeiRRJ #energy #estimation
- Energy Estimation for Extensible Processors (YF, SR, AR, NKJ), pp. 10682–10687.
- DATE-2003-RaghunathanRHQ #challenge #design #mobile
- Securing Mobile Appliances: New Challenges for the System Designer (AR, SR, SH, JJQ), pp. 10176–10183.
- DATE-2003-TanRJ #approach #architecture #embedded #energy
- Software Architectural Transformations: A New Approach to Low Energy Embedded Software (TKT, AR, NKJ), pp. 11046–11051.
- DAC-2002-LahiriDR #architecture #communication #design #performance #power management
- Communication architecture based power management for battery efficient system design (KL, SD, AR), pp. 691–696.
- DAC-2002-RaviRPS #design #framework #platform #security
- System design methodologies for a wireless security processing platform (SR, AR, NRP, MS), pp. 777–782.
- DAC-2001-LahiriRL #architecture #communication #design #named
- LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs (KL, AR, GL), pp. 15–20.
- DAC-2001-TanRLJ #energy #megamodelling
- High-level Software Energy Macro-modeling (TKT, AR, GL, NKJ), pp. 605–610.
- DAC-2001-WangRLJ #adaptation #design #energy #optimisation #performance
- Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization (WW, AR, GL, NKJ), pp. 738–743.
- DAC-2000-DickLRJ #analysis #embedded #operating system
- Power analysis of embedded operating systems (RPD, GL, AR, NKJ), pp. 312–315.
- DAC-2000-LahiriRLD #architecture #communication #design
- Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips (KL, AR, GL, SD), pp. 513–518.
- DATE-2000-LajoloRDL #design #performance
- Efficient Power Co-Estimation Techniques for System-on-Chip Design (ML, AR, SD, LL), pp. 27–34.
- DAC-1999-LakshminarayanaRKJD #optimisation #performance
- Common-Case Computation: A High-Level Technique for Power and Performance Optimization (GL, AR, KSK, NKJ, SD), pp. 56–61.
- DAC-1998-LakshminarayanaRJ #behaviour #control flow #execution #scheduling
- Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions (GL, AR, NKJ), pp. 108–113.
- DAC-1997-GhoshRJ #design #generative #testing
- Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs (IG, AR, NKJ), pp. 534–539.
- DAC-1997-RaghunathanDJW #control flow #design #power management
- Power Management Techniques for Control-Flow Intensive Designs (AR, SD, NKJ, KW), pp. 429–434.
- DAC-1996-RaghunathanDJ #analysis #reduction
- Glitch Analysis and Reduction in Register Transfer Level (AR, SD, NKJ), pp. 331–336.