BibSLEIGH — Erik_Jan

Travelled to:

2 × USA
4 × France
7 × Germany

Collaborated with:

S.K.Goel ∅ K.Chakrabarty Y.Zorian V.Iyengar O.Sinanoglu P.Wielage C.Wouters M.Taouil M.Masadeh S.Hamdioui M.Altheimer A.Sehgal B.Prince D.Keitel-Schulz K.Chiu T.Nguyen S.Oostdijk B.Vermeulen R.Madge M.Kessler M.Müller T.Dubois M.Azimane E.Larsson G.Vandling F.Hapke J.Rivers N.Mittermaier S.Bahl D.Y.Lee J.P.Hayes C.Sellathamby B.Moore S.Slupsky L.Pujol A.Singh D.Glotter M.Esposito J.M.C.Jr. A.Nahar K.M.Butler D.Appello C.Portelli

Talks about:

test (18) design (7) chip (5) system (4) soc (4) infrastructur (3) effici (3) stack (3) optim (3) embed (3)

Person: Erik Jan Marinissen

DBLP: Marinissen:Erik_Jan

Contributed to:

2014

2012

2010

2009

2008

2007

2006

2005

2004

2003

2002

2000

Wrote 18 papers:

DATE-2014-TaouilMHM #3d: Interconnect test for 3D stacked memory-on-logic (MT, MM, SH, EJM), pp. 1–6.
DATE-2012-Marinissen #2d #3d #challenge #testing: Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs (EJM), pp. 1277–1282.
DATE-2012-MarinissenVGHRMB #detection #process: EDA solutions to new-defect detection in advanced process technologies (EJM, GV, SKG, FH, JR, NM, SB), pp. 123–128.
DATE-2010-Marinissen #3d #testing: Testing TSV-based three-dimensional stacked ICs (EJM), pp. 1689–1694.
DATE-2010-MarinissenSGECNBAP #adaptation #testing: Adapting to adaptive testing (EJM, AS, DG, ME, JMCJ, AN, KMB, DA, CP), pp. 556–561.
DATE-2009-MarinissenLHSMSP #question #testing: Contactless testing: Possibility or pipe-dream? (EJM, DYL, JPH, CS, BM, SS, LP), pp. 676–681.
DATE-2008-SinanogluM #analysis #composition #reduction #testing: Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing (OS, EJM), pp. 182–187.
DATE-2007-DuboisMAWLW #analysis #embedded #quality: Test quality analysis and improvement for an embedded asynchronous FIFO (TD, EJM, MA, PW, EL, CW), pp. 859–864.
DATE-2007-WielageMAW #design #embedded #performance: Design and DfT of a high-speed area-efficient embedded asynchronous FIFO (PW, EJM, MA, CW), pp. 853–858.
DATE-2006-SehgalGMC #design #framework: Hierarchy-aware and area-efficient test infrastructure design for core-based system chips (AS, SKG, EJM, KC), pp. 285–290.
DATE-2005-GoelM #design #framework #multi #testing: On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips (SKG, EJM), pp. 44–49.
DATE-2005-MarinissenPKZ #challenge #design #embedded #memory management: Challenges in Embedded Memory Design and Test (EJM, BP, DKS, YZ), pp. 722–727.
DATE-DF-2004-GoelCMNO #design #framework: Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip (SKG, KC, EJM, TN, SO), pp. 108–113.
DATE-2003-GoelM #architecture #design: Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization (SKG, EJM), pp. 10738–10741.
DATE-2003-MarinissenVMKM: Creating Value Through Test (EJM, BV, RM, MK, MM), pp. 10402–10409.
DAC-2002-IyengarCM #constraints #reduction #scheduling: Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs (VI, KC, EJM), pp. 685–690.
DATE-2002-IyengarCM #performance #scalability: Efficient Wrapper/TAM Co-Optimization for Large SOCs (VI, KC, EJM), pp. 491–498.
DAC-2000-ZorianM #design #how #question: System chip test: how will it impact your design? (YZ, EJM), pp. 136–141.