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Travelled to:
1 × France
2 × Germany
7 × USA
Collaborated with:
V.Balakrishnan K.Roy R.Lu A.Cao G.Zhong P.Sarkar R.Ewetz S.Janarthanan W.Liu Y.Li W.Chai D.Jiao N.Wong Q.Su Y.Chen K.Chao R.Zhang D.B.Janes
Talks about:
interconnect (3) reduct (3) model (3) plan (3) preserv (2) extract (2) repeat (2) passiv (2) integr (2) effici (2)

Person: Cheng-Kok Koh

DBLP DBLP: Koh:Cheng=Kok

Contributed to:

DAC 20152015
DAC 20132013
DAC 20092009
DAC 20042004
DAC 20032003
DATE 20032003
DAC 20022002
DATE 20022002
DAC 20012001
DATE 20012001

Wrote 12 papers:

DAC-2015-EwetzJK #configuration management #design
Construction of reconfigurable clock trees for MCMM designs (RE, SJ, CKK), p. 6.
DAC-2013-LiuKL #optimisation
Optimization of placement solutions for routability (WHL, CKK, YLL), p. 9.
DAC-2009-ChaiJK #3d #complexity #equation #linear #scalability
A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction (WC, DJ, CKK), pp. 752–757.
DAC-2004-CaoK #logic #optimisation
Post-layout logic optimization of domino circuits (AC, CKK), pp. 820–825.
DAC-2004-WongBK #performance #reduction
Passivity-preserving model reduction via a computationally efficient project-and-balance scheme (NW, VB, CKK), pp. 369–374.
DAC-2003-ZhongKBR #adaptation #implementation #performance
An adaptive window-based susceptance extraction and its efficient implementation (GZ, CKK, VB, KR), pp. 728–731.
DATE-2003-LuK
Interconnect Planning with Local Area Constrained Retiming (RL, CKK), pp. 10442–10447.
DAC-2002-SuBK #framework #reduction
A factorization-based framework for passivity-preserving model reduction of RLC systems (QS, VB, CKK), pp. 40–45.
DATE-2002-ChenBKR #reduction #using
Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods (YC, VB, CKK, KR), pp. 931–935.
DATE-2002-LuZKC
Flip-Flop and Repeater Insertion for Early Interconnect Planning (RL, GZ, CKK, KYC), pp. 690–695.
DAC-2001-ZhangRKJ #3d #architecture #integration
Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration (RZ, KR, CKK, DBJ), pp. 846–851.
DATE-2001-SarkarK #constraints
Repeater block planning under simultaneous delay and transition time constraints (PS, CKK), pp. 540–545.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.