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Travelled to:
1 × France
2 × USA
Collaborated with:
Y.Xie J.Li G.Sun X.Dong L.Zhang E.Speight H.H.Li Y.Chen R.Das C.R.Das
Talks about:
memori (2) microarchitectur (1) interconnect (1) volatil (1) univers (1) perform (1) circuit (1) replac (1) magnet (1) integr (1)

Person: Xiaoxia Wu

DBLP DBLP: Wu:Xiaoxia

Contributed to:

DAC 20102010
DATE 20092009
DAC 20082008

Wrote 3 papers:

DAC-2010-WuSDDXDL #3d #integration
Cost-driven 3D integration with interconnect layers (XW, GS, XD, RD, YX, CRD, JL), pp. 150–155.
DATE-2009-WuLZSX #hybrid #performance
Power and performance of read-write aware Hybrid Caches with non-volatile memories (XW, JL, LZ, ES, YX), pp. 737–742.
DAC-2008-DongWSXLC #3d #architecture #evaluation #memory management #ram
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement (XD, XW, GS, YX, HHL, YC), pp. 554–559.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.