Travelled to:1 × China
1 × Germany
2 × France
4 × USA
Collaborated with:Y.Xie J.Wang G.Sun J.Zhao N.P.Jouppi Y.Chen J.Li X.Wu C.Xu Y.Joo D.Niu N.Chang H.H.Li R.Das C.R.Das
Talks about:cach (6) design (4) awar (3) architectur (2) volatil (2) memori (2) energi (2) stack (2) point (2) level (2)
Person: Xiangyu Dong
DBLP: Dong:Xiangyu
Contributed to:
2013
2013
201220112010201020092008Wrote 10 papers:
- DATE-2013-WangDX #named #policy
- OAP: an obstruction-aware cache management policy for STT-RAM last-level caches (JW, XD, YX), pp. 847–852.
- HPCA-2013-WangDXJ #named
- i2WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations (JW, XD, YX, NPJ), pp. 234–245.
- DAC-2012-WangDX #architecture
- Point and discard: a hard-error-tolerant architecture for non-volatile last level caches (JW, XD, YX), pp. 253–258.
- DATE-2011-XuDJX #design
- Design implications of memristor-based RRAM cross-point structures (CX, XD, NPJ, YX), pp. 734–739.
- DATE-2011-ZhaoDX #3d #design #energy #fine-grained #scalability
- An energy-efficient 3D CMP design with fine-grained voltage scaling (JZ, XD, YX), pp. 539–542.
- DAC-2010-WuSDDXDL #3d #integration
- Cost-driven 3D integration with interconnect layers (XW, GS, XD, RD, YX, CRD, JL), pp. 150–155.
- DAC-2010-ZhaoDX #3d #cost analysis #design #manycore
- Cost-aware three-dimensional (3D) many-core multiprocessor design (JZ, XD, YX), pp. 126–131.
- DATE-2010-JooNDSCX #design #energy #memory management
- Energy- and endurance-aware design of phase change memory caches (YJ, DN, XD, GS, NC, YX), pp. 136–141.
- HPCA-2009-SunDXLC #3d #architecture #novel
- A novel architecture of the 3D stacked MRAM L2 cache for CMPs (GS, XD, YX, JL, YC), pp. 239–249.
- DAC-2008-DongWSXLC #3d #architecture #evaluation #memory management #ram
- Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement (XD, XW, GS, YX, HHL, YC), pp. 554–559.