Travelled to:
1 × France
1 × Korea
13 × USA
Collaborated with:
A.Sivasubramaniam A.K.Mishra A.S.Vaidya M.T.Kandemir R.Iyer Y.M.Boura R.Das O.Mutlu K.H.Yum N.Vijaykrishnan M.Jung D.Park M.S.Yousif Y.Xie N.C.Nachiappan A.Jog V.Narayanan S.Eachempati J.Kim T.Theocharides E.J.Kim J.Duato S.Chodnekar V.Srinivasan Chun-Yi Liu Jagadish B. Kotra S.Yi B.Kim J.Oh J.Jang G.Kesidis Nima Elyasi M.Arjomand P.Yedlapalli N.Soundararajan C.Xu X.Wu G.Sun X.Dong J.Li O.Kayiran C.Nicopoulos R.R.Iyer X.Jiang L.Zhao Z.Fang S.Srinivasan S.Makineni P.Brett
Talks about:
perform (6) chip (4) interconnect (3) router (3) design (3) cmps (3) cach (3) architectur (2) techniqu (2) support (2)
Person: Chita R. Das
DBLP: Das:Chita_R=
Facilitated 1 volumes:
Contributed to:
Wrote 17 papers:
- HPCA-2015-NachiappanYSSKI #energy #knowledge base
- Domain knowledge based energy management in handhelds (NCN, PY, NS, AS, MTK, RI, CRD), pp. 150–160.
- ASPLOS-2013-JogKNMKMID #array #concurrent #named #owl #performance #scheduling #thread
- OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance (AJ, OK, NCN, AKM, MTK, OM, RI, CRD), pp. 395–406.
- DAC-2013-MishraMD #approach #design #multi
- A heterogeneous multiple network-on-chip design: an application-aware approach (AKM, OM, CRD), p. 10.
- DAC-2012-JogMXXNID #architecture #performance
- Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs (AJ, AKM, CX, YX, VN, RI, CRD), pp. 243–252.
- HPCA-2011-JiangMZIFSMBD #named #scheduling #symmetry
- ACCESS: Smart scheduling for asymmetric cache CMPs (XJ, AKM, LZ, RI, ZF, SS, SM, PB, CRD), pp. 527–538.
- DAC-2010-WuSDDXDL #3d #integration
- Cost-driven 3D integration with interconnect layers (XW, GS, XD, RD, YX, CRD, JL), pp. 150–155.
- HPCA-2009-DasEMVD #design #evaluation
- Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs (RD, SE, AKM, NV, CRD), pp. 175–186.
- HPCA-2008-DasMNPNIYD #architecture #optimisation #performance
- Performance and power optimization through data compression in Network-on-Chip architectures (RD, AKM, CN, DP, VN, RRI, MSY, CRD), pp. 215–225.
- SAC-2007-YiKOJKD #detection #hardware #performance
- Memory-efficient content filtering hardware for high-speed intrusion detection systems (SY, BKK, JO, JJ, GK, CRD), pp. 264–269.
- DAC-2005-KimPTVD #adaptation #latency
- A low latency router supporting adaptivity for on-chip interconnects (JK, DP, TT, NV, CRD), pp. 559–564.
- HPCA-2003-KimYDYD #architecture #performance
- Performance Enhancement Techniques for InfiniBand? Architecture (EJK, KHY, CRD, MSY, JD), pp. 253–262.
- HPCA-2000-YumVDS
- Investigating QoS Support for Traffic Mixes with the MediaWorm Router (KHY, ASV, CRD, AS), pp. 97–106.
- HPCA-1999-VaidyaSD #adaptation #design #named #performance
- LAPSES: A Recipe for High Performance Adaptive Router Design (ASV, AS, CRD), pp. 236–243.
- HPCA-1997-ChodnekarSVSD #communication #parallel #towards
- Towards a Communication Characterization Methodology for Parallel Applications (SC, VS, ASV, AS, CRD), pp. 310–319.
- HPCA-1995-BouraD #modelling
- Modeling Virtual Channel Flow Control in Hypercubes (YMB, CRD), pp. 166–175.
- ASPLOS-2017-ElyasiASKDJ #performance
- Exploiting Intra-Request Slack to Improve SSD Performance (NE, MA, AS, MTK, CRD, MJ), pp. 375–388.
- ASPLOS-2019-LiuKJKD #3d
- SOML Read: Rethinking the Read Operation Granularity of 3D NAND SSDs (CYL, JBK, MJ, MTK, CRD), pp. 955–969.