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Travelled to:
1 × France
3 × USA
Collaborated with:
L.He F.Li Y.Hu T.Tuan L.Cheng P.Wong
Talks about:
reduct (5) power (5) fpga (5) dual (4) vdd (4) assign (2) slack (2) time (2) interconnect (1) architectur (1)

Person: Yan Lin


Contributed to:

DATE 20072007
DAC 20062006
DAC 20052005
DAC 20042004

Wrote 5 papers:

DATE-2007-LinH #interactive #reduction #statistics
Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction (YL, LH), pp. 636–641.
DAC-2006-HuLHT #reduction
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction (YH, YL, LH, TT), pp. 478–483.
DAC-2005-ChengWLLH #architecture #reduction
Device and architecture co-optimization for FPGA power reduction (LC, PW, FL, YL, LH), pp. 915–920.
DAC-2005-LinH #performance #reduction
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction (YL, LH), pp. 720–725.
DAC-2004-LiLH #configuration management #reduction #using
FPGA power reduction using configurable dual-Vdd (FL, YL, LH), pp. 735–740.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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