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Travelled to:
2 × France
4 × Germany
5 × USA
Collaborated with:
X.Li L.He J.Ye R.Majumdar X.Hu S.Pan K.Huang B.Li S.Shan G.Yan X.Zhang M.Jose V.Shih J.Li Q.Xu Y.Lin T.Tuan S.Roy A.Pandey B.Dolan-Gavitt S.B.Luckenbill J.Lee Y.Xu J.Ma G.Chen Y.Xie B.Liu H.Liu J.Gong Y.Liu S.Hu J.Wu Y.Shi Y.Jin
Talks about:
fault (5) power (4) base (4) reduct (3) impact (3) fpga (3) diagnosi (2) multipl (2) voltag (2) thread (2)

Person: Yu Hu


Contributed to:

DAC 20152015
DAC 20142014
DATE 20142014
DATE 20132013
DATE 20122012
DATE 20112011
DAC 20102010
DATE 20102010
DAC 20082008
DATE 20082008
DAC 20062006
ESEC/FSE 20182018

Wrote 17 papers:

DAC-2015-LiuHWSJHL #assessment #detection #smarttech
Impact assessment of net metering on smart home cyberattack detection (YL, SH, JW, YS, YJ, YH, XL), p. 6.
DAC-2014-HuXMCHX #thread
Thermal-Sustainable Power Budgeting for Dynamic Threading (XH, YX, JM, GC, YH, YX), p. 6.
DATE-2014-LiSH0 #in memory #memory management #named
Partial-SET: Write speedup of PCM main memory (BL, SS, YH, XL), pp. 1–4.
DATE-2013-HuYH0 #concurrent #low cost #multi #named #thread
Orchestrator: a low-cost solution to reduce voltage emergencies for multi-threaded applications (XH, GY, YH, XL), pp. 208–213.
DATE-2013-ZhangYH0 #testing
Capturing post-silicon variation by layout-aware path-delay testing (XZ, JY, YH, XL), pp. 288–291.
DATE-2012-HuangHLLLG #power management
Off-path leakage power aware routing for SRAM-based FPGAs (KH, YH, XL, BL, HL, JG), pp. 87–92.
DATE-2011-HuangHL #fault
Cross-layer optimized placement and routing for FPGA soft error mitigation (KH, YH, XL), pp. 58–63.
DATE-2011-PanHHL #effectiveness
A cost-effective substantial-impact-filter based method to tolerate voltage emergencies (SP, YH, XH, XL), pp. 311–315.
DATE-2011-YeHL #fault #multi #on the #using
On diagnosis of multiple faults using compacted responses (JY, YH, XL), pp. 679–684.
DAC-2010-JoseHMH #robust
Rewiring for robustness (MJ, YH, RM, LH), pp. 469–474.
DATE-2010-LuckenbillLHMH #algorithm #analysis #fault #logic #named #reliability
RALF: Reliability Analysis for Logic Faults — An exact algorithm and its applications (SBL, JYL, YH, RM, LH), pp. 783–788.
DATE-2010-PanHL #fault #named
IVF: Characterizing the vulnerability of microprocessor structures to intermittent faults (SP, YH, XL), pp. 238–243.
DATE-2010-YeHL #fault #multi
Diagnosis of multiple arbitrary faults with mask and reinforcement effect (JY, YH, XL), pp. 885–890.
DAC-2008-HuSMH #multi #reduction
FPGA area reduction by multi-output function based sequential resynthesis (YH, VS, RM, LH), pp. 24–29.
DATE-2008-LiXHL #named #reduction #testing
iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing (JL, QX, YH, XL), pp. 1184–1189.
DAC-2006-HuLHT #reduction
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction (YH, YL, LH, TT), pp. 478–483.
ESEC-FSE-2018-RoyPDH #debugging #fault #synthesis #tool support
Bug synthesis: challenging bug-finding tools with deep faults (SR, AP, BDG, YH), pp. 224–234.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.