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Travelled to:
1 × China
2 × Germany
7 × USA
Collaborated with:
T.Mitra H.Ding Y.Wang D.Chen X.Xie G.Sun T.Wang X.Chen Y.Xie H.Yang A.Papakonstantinou W.W.Hwu J.Cong H.Song Y.Qi H.Peng L.Zhang W.T.Tang R.Zhao M.Lu H.P.Huyng X.Li R.S.M.Goh Z.Cui S.Zhao K.Rupnow Y.Zhang D.L.Jones
Talks about:
cach (6) instruct (4) time (4) lock (4) optim (3) centric (2) analysi (2) dynam (2) wcet (2) real (2)

Person: Yun Liang

DBLP DBLP: Liang:Yun

Contributed to:

CGO 20152015
HPCA 20152015
DAC 20142014
DATE 20142014
DAC 20132013
DAC 20122012
DATE 20122012
DAC 20102010
DAC 20082008
HCI/HIMI p1 20072007

Wrote 11 papers:

CGO-2015-TangZLLHLG #multi #optimisation
Optimizing and auto-tuning scale-free sparse matrix-vector multiplication on Intel Xeon Phi (WTT, RZ, ML, YL, HPH, XL, RSMG), pp. 136–145.
HPCA-2015-XieLWSW #coordination
Coordinated static and dynamic cache bypassing for GPUs (XX, YL, YW, GS, TW), pp. 76–88.
DAC-2014-ChenWLXY #optimisation #runtime
Run-Time Technique for Simultaneous Aging and Power Optimization in GPGPUs (XC, YW, YL, YX, HY), p. 6.
DATE-2014-DingLM
WCET-Centric dynamic instruction cache locking (HD, YL, TM), pp. 1–6.
DAC-2013-DingLM #analysis #multi #realtime
Integrated instruction cache analysis and locking in multitasking real-time systems (HD, YL, TM), p. 10.
DAC-2013-PapakonstantinouCHCL #kernel #migration
Throughput-oriented kernel porting onto FPGAs (AP, DC, WmWH, JC, YL), p. 10.
DAC-2012-DingLM
WCET-centric partial instruction cache locking (HD, YL, TM), pp. 412–420.
DATE-2012-LiangCZRZJC #3d #implementation #locality #optimisation #performance #realtime
Real-time implementation and performance optimization of 3D sound localization on GPUs (YL, ZC, SZ, KR, YZ, DLJ, DC), pp. 832–835.
DAC-2010-LiangM #reuse #using
Instruction cache locking using temporal reuse profile (YL, TM), pp. 344–349.
DAC-2008-LiangM #analysis #execution #modelling #probability
Cache modeling in probabilistic execution time analysis (YL, TM), pp. 319–324.
HIMI-MTT-2007-SongQLPZ #linear #named #navigation
LensList: Browsing and Navigating Long Linear Information Structures (HS, YQ, YL, HP, LZ), pp. 535–543.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.