BibSLEIGH — Tulika

Travelled to:

14 × USA
3 × France
3 × Germany

Collaborated with:

Y.Liang A.Roychoudhury H.P.Huynh H.Ding L.Chen R.Jayaseelan V.Suhendra A.Pathania T.S.Muthukaruppan Q.Jiao Z.Ge P.Yu T.Marconi W.Wong H.Liu X.Li S.R.Karri A.Goel M.Lu A.Prakash U.D.Bordoloi S.Chakraborty T.N.Dang P.Mishra T.Chen M.Pricopi V.Venkataramani S.Vishin Y.Yao G.Wang W.Chen N.Zhang

Talks about:

instruct (9) cach (8) time (6) core (6) multi (5) lock (5) reconfigur (4) analysi (4) system (4) manag (4)

Person: Tulika Mitra

DBLP: Mitra:Tulika

Contributed to:

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2004

2003

2002

Wrote 26 papers:

CGO-2015-JiaoLHM #concurrent #energy #execution #kernel: Improving GPGPU energy-efficiency through concurrent kernel execution and DVFS (QJ, ML, HPH, TM), pp. 1–11.
DATE-2015-YaoWGMCZ #architecture #manycore #named: SelectDirectory: a selective directory for cache coherence in many-core architectures (YY, GW, ZG, TM, WC, NZ), pp. 175–180.
ASPLOS-2014-MuthukaruppanPM #multi #power management: Price theory based power management for heterogeneous multi-cores (TSM, AP, TM), pp. 161–176.
DAC-2014-PathaniaJPM #3d #cpu #game studies #gpu #mobile #power management: Integrated CPU-GPU Power Management for 3D Mobile Games (AP, QJ, AP, TM), p. 6.
DATE-2014-DingLM: WCET-Centric dynamic instruction cache locking (HD, YL, TM), pp. 1–6.
DAC-2013-DingLM #analysis #multi #realtime: Integrated instruction cache analysis and locking in multitasking real-time systems (HD, YL, TM), p. 10.
DAC-2013-MuthukaruppanPVMV #manycore #power management #symmetry: Hierarchical power management for asymmetric multi-core in dark silicon era (TSM, MP, VV, TM, SV), p. 9.
DAC-2012-DingLM: WCET-centric partial instruction cache locking (HD, YL, TM), pp. 412–420.
DATE-2012-ChenMM #configuration management #manycore #online #scheduling: Online scheduling for multi-core shared reconfigurable fabric (LC, TM, TM), pp. 582–585.
DAC-2011-ChenM #configuration management #manycore: Shared reconfigurable fabric for multi-core customization (LC, TM), pp. 830–835.
DAC-2010-LiangM #reuse #using: Instruction cache locking using temporal reuse profile (YL, TM), pp. 344–349.
DAC-2009-BordoloiHCM #design #trade-off: Evaluating design trade-offs in customizable processors (UDB, HPH, SC, TM), pp. 244–249.
DAC-2009-DangRMM #generative #interactive #pipes and filters #source code: Generating test programs to cover pipeline interactions (TND, AR, TM, PM), pp. 142–147.
DAC-2009-GeMW #configuration management #memory management #pipes and filters: A DVS-based pipelined reconfigurable instruction memory (ZG, TM, WFW), pp. 897–902.
DAC-2009-JayaseelanM #adaptation #architecture: Dynamic thermal management via architectural adaptation (RJ, TM), pp. 484–489.
DATE-2009-HuynhM #configuration management #embedded #realtime #runtime: Runtime reconfiguration of custom instructions for real-time embedded systems (HPH, TM), pp. 1536–1541.
DAC-2008-LiangM #analysis #execution #modelling #probability: Cache modeling in probabilistic execution time analysis (YL, TM), pp. 319–324.
DAC-2008-SuhendraM #clustering #multi #predict: Exploring locking & partitioning for predictable shared caches on multi-cores (VS, TM), pp. 300–303.
DATE-2007-HuynhM #embedded #realtime: Instruction-set customization for real-time embedded systems (HPH, TM), pp. 1472–1477.
DAC-2006-JayaseelanLM: Exploiting forwarding to improve data bandwidth of instruction-set extensions (RJ, HL, TM), pp. 43–48.
DAC-2006-SuhendraMRC #analysis #detection #performance: Efficient detection and exploitation of infeasible paths for software timing analysis (VS, TM, AR, TC), pp. 358–363.
DAC-2004-YuM #embedded: Characterizing embedded applications for instruction-set extensible processors (PY, TM), pp. 723–728.
DAC-2003-LiMR #analysis #interactive #modelling: Accurate timing analysis by modeling caches, speculation and their interaction (XL, TM, AR), pp. 466–471.
DATE-2003-RoychoudhuryMK #debugging #protocol #using: Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol (AR, TM, SRK), pp. 10828–10833.
PPoPP-2003-GoelRM #parallel #representation: Compactly representing parallel program executions (AG, AR, TM), pp. 191–202.
ICSE-2002-RoychoudhuryM #java #parallel #semantics #specification #thread #verification: Specifying multithreaded Java semantics for program verification (AR, TM), pp. 489–499.