35 papers:
DHM-EH-2015-KollingKHC #design #evaluation #feedback #interactive #process #using- Estimating Ergonomic Comfort During the Process of Mechanism Design by Interaction with a Haptic Feedback-System — Evaluation of Simulated and Kinesthetically Displayed Mechanisms Using the Haptic Feedback System RePlaLink (TK, MK, MH, BC), pp. 62–73.
SPLC-2009-HendricksonWHTK #modelling #personalisation #privacy- Modeling PLA variation of privacy-enhancing personalized systems (SAH, YW, AvdH, RNT, AK), pp. 71–80.
DATE-2007-AngioliniJABM #design #fault tolerance #interactive- Interactive presentation: Improving the fault tolerance of nanometric PLA designs (FA, MHBJ, DA, LB, GDM), pp. 570–575.
VLDB-2007-Chen0LLY #performance #similarity- Indexable PLA for Efficient Similarity Search (QC, LC, XL, YL, JXY), pp. 435–446.
DAC-2006-JayakumarGGK #approach #design- A PLA based asynchronous micropipelining approach for subthreshold circuit design (NJ, RG, BG, SPK), pp. 419–424.
- SPLC-2006-WangKHW #personalisation #privacy #runtime #web
- PLA-based Runtime Dynamism in Support of Privacy-Enhanced Web Personalization (YW, AK, AvdH, JW), pp. 151–162.
- DATE-v2-2004-LiuWH #logic #synthesis
- Crosstalk Minimization in Logic Synthesis for PLA (YYL, KHW, TH), pp. 790–795.
- SPLC-2004-StegerTBMPSF #case study #experience
- Introducing PLA at Bosch Gasoline Systems: Experiences and Practices (MS, CT, BB, AM, OP, WS, SF), pp. 34–50.
- DATE-2003-KrausP #flexibility #named #synthesis
- XBM2PLA: A Flexible Synthesis Tool for Extended Burst Mode Machines (OK, MP), pp. 11092–11093.
SAC-1994-Li #equivalence #graph #on the- On the equivalence of pull-up transistor assignment in PLA folding and distribution graph (WNL), pp. 374–378.
- DAC-1989-Paulin #clustering #finite #state machine
- Horizontal Partitioning of PLA-based Finite State Machines (PGP), pp. 333–338.
- DAC-1988-WehnGCMR
- A Defect-Tolerant and Fully Testable PLA (NW, MG, KC, PM, AR), pp. 22–33.
- DAC-1987-GalivancheR #parallel
- A Parallel PLA Minimization Program (RG, SMR), pp. 600–607.
- DAC-1987-LiuSU #array #design #logic #named #programmable #scalability #self
- BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays (CYL, KKS, SJU), pp. 385–391.
- DAC-1987-LursinsapG
- Improving a PLA Area by Pull-Up Transistor Folding (CL, DG), pp. 608–614.
- DAC-1986-Daehn #difference #fault
- A unified treatment of PLA faults by Boolean differences (WD), pp. 334–338.
- DAC-1986-Gerveshi #comparison #logic
- Comparison of CMOS PLA and polycell representations of control logic (CMG), pp. 638–642.
- DAC-1986-LigthartAB #statistics #using
- Design-for-testability of PLA’s using statistical cooling (MML, EHLA, FPMB), pp. 339–345.
- DAC-1985-BreuerZ #knowledge base
- A knowledge based system for selecting a test methodology for a PLA (MAB, XaZ), pp. 259–265.
- DAC-1985-KosekiY #design #named
- PLAYER: a PLA design system for VLSI’s (YK, TY), pp. 766–769.
- DAC-1985-KuoCH #algorithm #heuristic
- A heuristic algorithm for PLA block folding (YSK, CC, TCH), pp. 744–747.
- DAC-1985-ObermeierK #approach
- PLA driver selection: an analytic approach (FWO, RHK), pp. 798–802.
- DAC-1985-WeiS #generative #named
- PLATYPUS: a PLA test pattern generation tool (RSW, ALSV), pp. 197–203.
- DAC-1984-LewandowskiL #algorithm #bound #branch
- A branch and bound algorithm for optimal pla folding (JLL, CLL), pp. 426–433.
- DAC-1983-LiuA #bound
- Bounds on the saved area ratio due to PLA folding (WL, DEA), pp. 538–544.
- DAC-1983-Martinez-CarballidoP #named #reduction
- PRONTO: Quick PLA product reduction (JMC, VMP), pp. 545–552.
- DAC-1983-SomenziGMP #testing #verification
- A new integrated system for PLA testing and verification (FS, SG, MM, PP), pp. 57–63.
- DAC-1983-StebniskyMWPF #automation #named #synthesis
- APSS: An automatic PLA synthesis system (MWS, MJM, JCW, RP, AF), pp. 430–435.
- DAC-1983-WimerS #optimisation #synthesis
- HOPLA-PLA optimization and synthesis (SW, NS), pp. 790–794.
- DAC-1982-EganL
- Optimal bipartite folding of PLA (JRE, CLL), pp. 141–146.
- DAC-1982-Grass #algorithm #bound
- A depth-first branch-and-bound algorithm for optimal PLA folding (WG), pp. 133–140.
- DAC-1982-TeelW #design #logic
- A logic minimizer for VLSI PLA design (BT, DW), pp. 156–162.
- DAC-1981-KangC #automation #synthesis
- Automatic PLA synthesis from a DDL-P description (SK, WMvC), pp. 391–397.
- DAC-1981-Paillotin #optimisation
- Optimization of the PLA area (JFP), pp. 406–410.
- DAC-1981-SuwaK
- A computer-aided-design system for segmented-folded PLA macro-cells (IS, WJK), pp. 398–405.
