BibSLEIGH — Kaustav

Travelled to:

10 × USA
2 × Germany

Collaborated with:

H.F.Dadgour N.Srivastava A.Mehrotra R.Suaya S.Lin C.Kshirsagar M.N.El-Zeftawi B.Agrawal T.Sherwood R.V.Joshi M.M.Hussain C.Smith A.H.Ajami M.Pedram L.P.P.P.v.Ginneken S.J.Souri K.Saraswat A.L.Sangiovanni-Vincentelli C.Hu A.Basu V.Wason A.M.Ionescu M.J.Declercq S.Mahapatra J.Gautier S.Mysore G.L.Loi

Talks about:

perform (7) analysi (7) interconnect (6) high (5) circuit (4) design (4) frequenc (3) effect (3) power (3) novel (3)

Person: Kaustav Banerjee

DBLP: Banerjee:Kaustav

Contributed to:

2010

2008

2007

2006

2004

2002

2001

2000

1999

Wrote 16 papers:

DAC-2010-DadgourHSB #analysis #design #energy #logic #using: Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS (HFD, MMH, CS, KB), pp. 893–896.
DATE-2010-DadgourB #architecture #design #detection #novel #pipes and filters #using: Aging-resilient design of pipelined architectures using novel detection and correction circuits (HFD, KB), pp. 244–249.
DATE-2010-SrivastavaSB #3d #performance: Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate (NS, RS, KB), pp. 459–464.
DAC-2008-KshirsagarEB #analysis #performance: Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs (CK, MNEZ, KB), pp. 250–255.
DATE-2008-SrivastavaSB #multi: High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate (NS, RS, KB), pp. 426–431.
DAC-2007-DadgourB #analysis #design #hybrid #power management: Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications (HFD, KB), pp. 306–311.
ASPLOS-2006-MysoreASLBS #3d: Introspective 3D chips (SM, BA, NS, SCL, KB, TS), pp. 264–273.
DAC-2006-BanerjeeS #future of #question: Are carbon nanotubes the future of VLSI interconnections? (KB, NS), pp. 809–814.
DAC-2006-DadgourJB #architecture #novel #power management: A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates (HFD, RVJ, KB), pp. 977–982.
DAC-2006-LoiASLSB #3d #analysis #performance: A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy (GLL, BA, NS, SCL, TS, KB), pp. 991–996.
DAC-2004-BasuLWMB #optimisation #power management: Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era (AB, SCL, VW, AM, KB), pp. 884–887.
DAC-2002-IonescuDMBG #hybrid #towards: Few electron devices: towards hybrid CMOS-SET integrated circuits (AMI, MJD, SM, KB, JG), pp. 88–93.
DAC-2001-AjamiBPG #analysis #performance: Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs (AHA, KB, MP, LPPPvG), pp. 567–572.
DAC-2001-BanerjeeM #analysis #distributed #novel #optimisation #performance #using: Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects (KB, AM), pp. 798–803.
DAC-2000-SouriBMS #analysis #design #motivation #multi #performance: Multiple Si layer ICs: motivation, performance analysis, and design implications (SJS, KB, AM, KS), pp. 213–220.
DAC-1999-BanerjeeMSH #on the: On Thermal Effects in Deep Sub-Micron VLSI Interconnects (KB, AM, ALSV, CH), pp. 885–891.