Travelled to:
1 × Canada
1 × China
1 × France
1 × Mexico
1 × Spain
1 × Turkey
16 × USA
Collaborated with:
S.Malik D.M.Brooks D.Lustig A.Bhattacharjee Y.Yetim P.Juang R.Joseph Z.Hu C.Isci ∅ Q.Wu D.W.Clark T.Liu Yipeng Huang 0001 Prakash Murali Ali Javadi-Abhari W.Jia K.A.Shaw S.Kaxiras F.Xie S.Ghosh Y.S.Li F.T.Chong S.Isaacman S.Ioannidis A.Chaintreau P.Zhong P.Ashar Geet Sethi David C. McKay G.Contreras J.Peng R.Ju G.Lueh Caroline Trippel Yatin A. Manerkar M.Pellauer Jonathan M. Baker H.Oki Y.Wang L.Peh D.Rubenstein J.Heckey S.Patil A.JavadiAbhari A.Holmes D.Kudrow K.R.Brown D.Franklin
Talks about:
comput (6) processor (5) quantum (5) parallel (4) softwar (4) control (4) voltag (4) scale (4) microprocessor (3) techniqu (3)
Person: Margaret Martonosi
DBLP: Martonosi:Margaret
Facilitated 1 volumes:
Contributed to:
Wrote 29 papers:
- ASPLOS-2015-HeckeyPJHKBFCM #communication #compilation #parallel #quantum
- Compiler Management of Communication and Parallelism for Quantum Computation (JH, SP, AJ, AH, DK, KRB, DF, FTC, MM), pp. 445–456.
- ASPLOS-2015-YetimMM #communication #execution #fault #named #parallel
- CommGuard: Mitigating Communication Errors in Error-Prone Parallel Execution (YY, SM, MM), pp. 311–323.
- HPCA-2014-JiaSM #memory management #named #parallel
- MRPB: Memory request prioritization for massively parallel processors (WJ, KAS, MM), pp. 272–283.
- DATE-2013-YetimMM #streaming
- Extracting useful computation from error-prone processors for streaming applications (YY, MM, SM), pp. 202–207.
- HPCA-2013-LustigM #cpu #fine-grained #gpu #latency
- Reducing GPU offload latency via fine-grained CPU-GPU synchronization (DL, MM), pp. 354–365.
- HPCA-2011-BhattacharjeeLM #multi
- Shared last-level TLBs for chip multiprocessors (AB, DL, MM), pp. 62–63.
- RecSys-2011-IsaacmanICM #distributed #predict #rating
- Distributed rating prediction in user generated content streams (SI, SI, AC, MM), pp. 69–76.
- ASPLOS-2010-BhattacharjeeM #multi
- Inter-core cooperative TLB for chip multiprocessors (AB, MM), pp. 359–370.
- HPCA-2006-IsciM
- Phase characterization for power: evaluating control-flow-based and event-counter-based techniques (CI, MM), pp. 121–132.
- LCTES-2006-Martonosi #case study #deployment #embedded #experience #hardware
- Embedded systems in the wild: ZebraNet software, hardware, and deployment experiences (MM), p. 1.
- HPCA-2005-WuJMC #adaptation #multi
- Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors (QW, PJ, MM, DWC), pp. 178–189.
- ASPLOS-2004-WuJMC #multi #online
- Formal online methods for voltage/frequency control in multiple clock domain microprocessors (QW, PJ, MM, DWC), pp. 248–259.
- HPCA-2004-JosephHM #analysis #case study #design #experience
- Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization (RJ, ZH, MM), pp. 36–47.
- LCTES-2004-ContrerasMPJL #named
- XTREM: a power simulator for the Intel XScale® core (GC, MM, JP, RJ, GYL), pp. 115–125.
- HPCA-2003-HuMK #correlation #named
- TCP: Tag Correlating Prefetchers (ZH, MM, SK), pp. 317–326.
- HPCA-2003-JosephBM #performance
- Control Techniques to Eliminate Voltage Emergencies in High Performance Processors (RJ, DMB, MM), pp. 79–90.
- PLDI-2003-XieMM #scalability
- Compile-time dynamic voltage scaling settings: opportunities and limits (FX, MM, SM), pp. 49–62.
- PPoPP-2003-LiuM #middleware #named #parallel
- Impala: a middleware system for managing autonomic, parallel sensor systems (TL, MM), pp. 107–118.
- ASPLOS-2002-JuangOWMPR #case study #design #energy #experience #trade-off
- Energy-efficient computing for wildlife tracking: design tradeoffs and early experiences with ZebraNet (PJ, HO, YW, MM, LSP, DR), pp. 96–107.
- HPCA-2001-BrooksM
- Dynamic Thermal Management for High-Performance Microprocessors (DMB, MM), pp. 171–182.
- HPCA-1999-BrooksM #performance
- Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance (DMB, MM), pp. 13–22.
- ASPLOS-1998-GhoshMM #analysis #precise #program transformation
- Precise Miss Analysis for Program Transformations with Caches of Arbitrary Associativity (SG, MM, SM), pp. 228–239.
- DAC-1998-ZhongAMM #case study #configuration management #problem #satisfiability #using
- Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability (PZ, PA, SM, MM), pp. 194–199.
- DAC-1997-MalikML #analysis #embedded
- Static Timing Analysis of Embedded Software (SM, MM, YTSL), pp. 147–152.
- PLATEAU-2018-HuangM #algorithm #named #quantum #source code #towards
- QDB: From Quantum Algorithms Towards Correct Quantum Programs (YH0, MM), p. 14.
- ASPLOS-2016-LustigSMB #interface #memory management #named #verification
- COATCheck: Verifying Memory Ordering at the Hardware-OS Interface (DL, GS, MM, AB), pp. 233–247.
- ASPLOS-2017-TrippelMLPM #hardware #memory management #named #verification
- TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA (CT, YAM, DL, MP, MM), pp. 119–133.
- ASPLOS-2019-MuraliBJCM #adaptation #compilation #quantum
- Noise-Adaptive Compiler Mappings for Noisy Intermediate-Scale Quantum Computers (PM, JMB, AJA, FTC, MM), pp. 1015–1029.
- ASPLOS-2020-MuraliMMJ #quantum
- Software Mitigation of Crosstalk on Noisy Intermediate-Scale Quantum Computers (PM, DCM, MM, AJA), pp. 1001–1016.