BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × United Kingdom
2 × Germany
3 × USA
5 × France
Collaborated with:
M.Balakrishnan A.Vishnoi N.D.Dutt A.Nicolau A.Kumar N.Sharma S.Chandran S.R.Sarangi V.Jain A.Sahu S.Kurra N.K.Singh G.R.Gupta M.Gupta J.Seo T.Kim A.Gangwar F.Alam N.Tripathi S.Narayan M.Li P.Agrawal F.Catthoor
Talks about:
processor (4) cach (4) applic (3) level (3) high (3) synthesi (2) control (2) memori (2) energi (2) effici (2)

Person: Preeti Ranjan Panda

DBLP DBLP: Panda:Preeti_Ranjan

Contributed to:

DATE 20142014
DATE 20132013
ECMFA 20112011
DAC 20092009
DATE 20092009
DATE 20072007
DAC 20062006
DATE 20052005
DAC 20022002
DATE 19981998
ED&TC 19971997

Wrote 13 papers:

DATE-2014-AlamPTSN #android #energy #optimisation
Energy optimization in Android applications through wakelock placement (FA, PRP, NT, NS, SN), pp. 1–4.
DATE-2014-SharmaPLAC #composition #data flow #energy #performance
Energy efficient data flow transformation for Givens Rotation based QR Decomposition (NS, PRP, ML, PA, FC), pp. 1–4.
DATE-2013-ChandranSP #validation
Space sensitive cache dumping for post-silicon validation (SC, SRS, PRP), pp. 497–502.
ECMFA-2011-JainKP #development #modelling #validation
A SysML Profile for Development and Early Validation of TLM 2.0 Models (VJ, AK, PRP), pp. 299–311.
DAC-2009-VishnoiPB #debugging #online
Online cache state dumping for processor debug (AV, PRP, MB), pp. 358–363.
DATE-2009-SahuBP #concurrent #estimation #framework #multi #performance #thread
A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors (AS, MB, PRP), pp. 1018–1023.
DATE-2009-VishnoiPB #debugging
Cache aware compression for processor debug support (AV, PRP, MB), pp. 208–213.
DATE-2007-KurraSP #synthesis
The impact of loop unrolling on controller delay in high level synthesis (SK, NKS, PRP), pp. 391–396.
DAC-2006-GuptaGP #agile #estimation #specification
Rapid estimation of control delay from high-level specifications (GRG, MG, PRP), pp. 455–458.
DATE-2005-GangwarBPK #architecture #clustering #evaluation
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures (AG, MB, PRP, AK), pp. 730–735.
DAC-2002-SeoKP #algorithm #memory management #synthesis
An integrated algorithm for memory allocation and assignment in high-level synthesis (JS, TK, PRP), pp. 608–611.
DATE-1998-PandaDN #embedded
Data Cache Sizing for Embedded Processor Applications (PRP, NDD, AN), pp. 925–926.
EDTC-1997-PandaDN #embedded #memory management #performance
Efficient utilization of scratch-pad memory in embedded processor applications (PRP, NDD, AN), pp. 7–11.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.