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Travelled to:
1 × Italy
1 × The Netherlands
18 × USA
2 × Canada
5 × Germany
7 × France
Collaborated with:
N.D.Dutt A.V.Veidenbaum P.Grun A.Kejariwal S.Gupta A.Aiken R.K.Gupta R.Gupta C.D.Polychronopoulos H.Wang R.Potasman R.Cornea P.R.Panda J.Hummel L.J.Hendren N.Dutt A.Shrivastava A.Halambi U.Banerjee J.A.Fisher J.R.Ellis J.C.Ruttenberg E.Earlie S.Sarma G.Li C.Badea D.Nicolaescu W.Tang D.J.Kolson N.Savoiu P.Mishra H.Tomiyama K.Siu J.Lis D.Gajski T.Muck L.A.D.Bathen P.Gupta N.Venkatasubramanian N.Bansal P.Biswas H.Saito N.Stavrakos S.Carroll R.Cammarota D.Donato M.Madhugiri S.Park Y.Paek S.Kim V.Ganesh A.Khare A.Azevedo I.Issenin T.Kam M.Kishinevsky S.Rotem X.Tian M.Girkar W.Li S.Kozhukhov Zhangxiaowen Gong Zhi Chen 0001 Justin Josef Szaday David C. Wong 0001 Z.Sura Neftali Watkinson S.Maleki D.A.Padua J.Torrellas
Talks about:
high (9) synthesi (8) compil (8) level (8) embed (7) explor (6) base (6) architectur (5) processor (5) parallel (5)

Person: Alexandru Nicolau

DBLP DBLP: Nicolau:Alexandru

Contributed to:

DAC 20152015
DATE 20152015
CC 20132013
PPoPP 20092009
LCTES 20082008
PPoPP 20082008
PPoPP 20072007
DATE 20062006
LCTES 20062006
DATE 20052005
PPoPP 20052005
DAC 20042004
DATE v1 20042004
DATE 20032003
DAC 20022002
DATE 20022002
DAC 20012001
DATE 20012001
DAC 20002000
DATE 20002000
CC 19991999
DATE 19991999
DATE 19981998
ED&TC 19971997
DAC 19941994
PLDI 19941994
DAC 19931993
PLDI 19921992
DAC 19911991
PPoPP 19911991
DAC 19901990
ESOP 19881988
PLDI 19881988
Best of PLDI 20041984
SCC 19841984
OOPSLA 20182018

Wrote 42 papers:

DAC-2015-SarmaMBDN #energy #linux #named #performance
SmartBalance: a sensing-driven linux load balancer for energy efficiency of heterogeneous MPSoCs (SS, TM, LADB, NDD, AN), p. 6.
DATE-2015-SarmaDGVN #paradigm #self
Cyberphysical-system-on-chip (CPSoC): a self-aware MPSoC paradigm with cross-layer virtual sensing and actuation (SS, NDD, PG, NV, AN), pp. 625–628.
CC-2013-CammarotaNVKDM #on the #optimisation
On the Determination of Inlining Vectors for Program Optimization (RC, AN, AVV, AK, DD, MM), pp. 164–183.
PPoPP-2009-NicolauLK #performance
Techniques for efficient placement of synchronization primitives (AN, GL, AK), pp. 199–208.
LCTES-2008-BadeaNV #embedded #energy #virtual machine
Impact of JVM superoperators on energy consumption in resource-constrained embedded systems (CB, AN, AVV), pp. 23–30.
PPoPP-2008-KejariwalNBVP #clustering
Cache-aware iteration space partitioning (AK, AN, UB, AVV, CDP), pp. 269–270.
PPoPP-2007-KejariwalTGLKBNVP #analysis #concurrent #cpu #performance #specification #thread #using
Tight analysis of the performance potential of thread speculation using spec CPU 2006 (AK, XT, MG, WL, SK, UB, AN, AVV, CDP), pp. 215–225.
DATE-2006-CorneaND #mobile #optimisation
Software annotations for power optimization on mobile devices (RC, AN, NDD), pp. 684–689.
LCTES-2006-ParkSDNPE #reduction #scheduling
Bypass aware instruction scheduling for register file power reduction (SP, AS, NDD, AN, YP, EE), pp. 173–181.
DATE-2005-ShrivastavaDNE #embedded #framework #named
PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors (AS, NDD, AN, EE), pp. 1264–1269.
PPoPP-2005-KejariwalNBP #approach #clustering #novel
A novel approach for partitioning iteration spaces with variable densities (AK, AN, UB, CDP), pp. 120–131.
DAC-2004-KejariwalGNDG #algorithm #clustering #energy #mobile
Proxy-based task partitioning of watermarking algorithms for reducing energy consumption in mobile devices (AK, SG, AN, ND, RG), pp. 556–561.
DATE-v1-2004-BansalGDNG #architecture #configuration management #network
Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures (NB, SG, ND, AN, RG), pp. 474–479.
DATE-v1-2004-GuptaDGN #control flow #design #synthesis
Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow (SG, ND, RG, AN), pp. 114–121.
DATE-2003-GuptaDGN #branch #design #synthesis
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs (SG, NDD, RKG, AN), pp. 10270–10275.
DATE-2003-NicolaescuVN #embedded #power management
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors (DN, AVV, AN), pp. 11064–11069.
DAC-2002-GuptaSDGNKKR #coordination #performance #synthesis
Coordinated transformations for high-level synthesis of high performance microprocessor blocks (SG, NS, NDD, RKG, AN, TK, MK, SR), pp. 898–903.
DATE-2002-AzevedoICGDVN #scheduling #using
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints (AA, II, RC, RG, NDD, AVV, AN), pp. 168–175.
DATE-2002-GrunDN #memory management
Memory System Connectivity Exploration (PG, NDD, AN), pp. 894–901.
DATE-2002-HalambiSBDN #compilation #performance #reduction #using
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs (AH, AS, PB, NDD, AN), pp. 402–408.
DATE-2002-MishraDNT #automation #execution #functional #multi #pipes and filters #verification
Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units (PM, NDD, AN, HT), pp. 36–43.
DATE-2002-TangGN #embedded #power management
Power Savings in Embedded Processors through Decode Filer Cache (WT, RKG, AN), pp. 443–448.
DAC-2001-GuptaSKDGN #design #synthesis
Speculation Techniques for High Level Synthesis of Control Intensive Designs (SG, NS, SK, NDD, RKG, AN), pp. 269–272.
DATE-2001-GrunDN #embedded #memory management #power management
Access pattern based local memory customization for low power embedded systems (PG, NDD, AN), pp. 778–784.
DAC-2000-GrunDN #compilation #memory management
Memory aware compilation through accurate timing extraction (PG, NDD, AN), pp. 316–321.
DATE-2000-HalambiCGDN #architecture
Architecture Exploration of Parameterizable EPIC SOC Architectures (AH, RC, PG, NDD, AN), p. 748.
CC-1999-SaitoSCPN #compilation #design
The Design of the PROMIS Compiler (HS, NS, SC, CDP, AN), pp. 214–228.
DATE-1999-HalambiGGKDN #architecture #compilation #named
EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability (AH, PG, VG, AK, NDD, AN), pp. 485–490.
DATE-1998-PandaDN #embedded
Data Cache Sizing for Embedded Processor Applications (PRP, NDD, AN), pp. 925–926.
EDTC-1997-PandaDN #embedded #memory management #performance
Efficient utilization of scratch-pad memory in embedded processor applications (PRP, NDD, AN), pp. 7–11.
DAC-1994-KolsonND #memory management #synthesis
Minimization of Memory Traffic in High-Level Synthesis (DJK, AN, NDD), pp. 149–154.
PLDI-1994-HummelHN #data flow #data type #dependence #pointer
A General Data Dependence Test for Dynamic, Pointer-Based Data Structures (JH, LJH, AN), pp. 218–229.
DAC-1993-WangDNS #architecture #multi #scalability #synthesis #using
High-Level Synthesis of Scalable Architectures for IIR Filters using Multichip Modules (HW, NDD, AN, KYS), pp. 336–342.
PLDI-1992-HendrenHN #abstraction #analysis #data type #imperative #pointer #recursion #source code
Abstractions for Recursive Pointer Data Structures: Improving the Analysis of Imperative Programs (LJH, JH, AN), pp. 249–260.
DAC-1991-NicolauP #incremental #reduction #synthesis
Incremental Tree Height Reduction for High Level Synthesis (AN, RP), pp. 770–774.
PPoPP-1991-NicolauW #bound #parallel
Optimal Schedules for Parallel Prefix Computation with Bounded Resources (AN, HW), pp. 1–10.
DAC-1990-PotasmanLNG #synthesis
Percolation Based Synthesis (RP, JL, AN, DG), pp. 444–449.
ESOP-1988-AikenN #parallel #pipes and filters
Perfect Pipelining: A New Loop Parallelization Technique (AA, AN), pp. 221–235.
PLDI-1988-AikenN #parallel
Optimal Loop Parallelization (AA, AN), pp. 308–317.
Best-of-PLDI-1984-FisherERN #compilation #parallel
Parallel processing: a smart compiler and a dumb machine (with retrospective) (JAF, JRE, JCR, AN), pp. 112–124.
SCC-1984-FisherERN #compilation #parallel
Parallel processing: a smart compiler and a dumb machine (JAF, JRE, JCR, AN), pp. 37–47.
OOPSLA-2018-GongCS0SWMPVNT #compilation #empirical
An empirical study of the effect of source-level loop transformations on compiler stability (ZG, ZC0, JJS, DCW0, ZS, NW, SM, DAP, AVV, AN, JT), p. 29.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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