Travelled to:1 × China
6 × USA
Collaborated with:D.Blaauw R.G.Dreslinski T.N.Mudge C.R.Das T.M.Austin R.Parikh V.Bertacco Daichi Fujiki S.A.Mahlke A.K.Mishra S.Jeloka N.Abeyratne W.Arthur B.Mehne R.Ausavarungnirun O.Mutlu A.Kumar M.Azimi S.Eachempati N.Vijaykrishnan S.Rao S.Satpathy D.Sylvester Y.Kang X.Wu G.Sun X.Dong Y.Xie J.Li Zelalem Birhanu Aweke Salessawi Ferede Yitbarek R.Qiao M.Hicks Yossi Oren Q.Li K.Sewell B.Giridhar C.Nicopoulos D.Park V.Narayanan R.R.Iyer M.S.Yousif
Talks about:control (3) switch (3) radix (3) high (3) data (3) core (3) interconnect (2) processor (2) topolog (2) qualiti (2)
Person: Reetuparna Das
DBLP: Das:Reetuparna
Contributed to:
2015
2014
20132012201020092008
20162018Wrote 12 papers:
- CGO-2015-ArthurMDA #control flow
- Getting in control of your control flow with control-data isolation (WA, BM, RD, TMA), pp. 79–90.
- DAC-2014-AbeyratneJKBDDM
- Quality-of-Service for a High-Radix Switch (NA, SJ, YK, DB, RGD, RD, TNM), p. 6.
- DAC-2014-ParikhDB #configuration management #power management
- Power-Aware NoCs through Routing and Topology Reconfiguration (RP, RD, VB), p. 6.
- DAC-2014-RaoJDBDM #named #performance
- VIX: Virtual Input Crossbar for Efficient Switch Allocation (SR, SJ, RD, DB, RGD, TNM), p. 6.
- HPCA-2013-AbeyratneDLSGDBM #scalability #symmetry #towards
- Scaling towards kilo-core processors with asymmetric high-radix topologies (NA, RD, QL, KS, BG, RGD, DB, TNM), pp. 496–507.
- HPCA-2013-DasAMKA #manycore #memory management #policy
- Application-to-core mapping policies to reduce memory system interference in multi-core systems (RD, RA, OM, AK, MA), pp. 107–118.
- DAC-2012-SatpathyDDMSB #multi #quality #self
- High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service (SS, RD, RGD, TNM, DS, DB), pp. 406–411.
- DAC-2010-WuSDDXDL #3d #integration
- Cost-driven 3D integration with interconnect layers (XW, GS, XD, RD, YX, CRD, JL), pp. 150–155.
- HPCA-2009-DasEMVD #design #evaluation
- Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs (RD, SE, AKM, NV, CRD), pp. 175–186.
- HPCA-2008-DasMNPNIYD #architecture #optimisation #performance
- Performance and power optimization through data compression in Network-on-Chip architectures (RD, AKM, CN, DP, VN, RRI, MSY, CRD), pp. 215–225.
- ASPLOS-2016-AwekeYQDHOA #named
- ANVIL: Software-Based Protection Against Next-Generation Rowhammer Attacks (ZBA, SFY, RQ, RD, MH, YO, TMA), pp. 743–755.
- ASPLOS-2018-FujikiMD #in memory #parallel
- In-Memory Data Parallel Processor (DF, SAM, RD), pp. 1–14.