BibSLEIGH — Guangyu

Travelled to:

1 × France
1 × India
3 × Germany
7 × USA

Collaborated with:

Y.Xie C.Xu X.Dong Y.Chen Y.Chen Y.Wang J.Li J.Zhan F.Wang Y.Liu H.Yang X.Wu Y.Joo D.Niu Q.Zou X.Xie Y.Liang T.Wang Z.Wang D.A.Jiménez T.Zhang M.Poremba H.Li Y.Gu C.Zhang N.Chang H.H.Li G.Li X.Chen H.Hoffmann R.Das C.R.Das H.Li Q.Zhao X.Sheng M.Chang R.Luo Y.Zhang W.Zhang Y.Sun J.Klein D.Ravelosona W.Zhao

Talks about:

memori (5) energi (4) cach (4) architectur (3) hybrid (3) design (3) awar (3) ram (3) interconnect (2) synthesi (2)

Person: Guangyu Sun

DBLP: Sun:Guangyu

Contributed to:

2015

2014

2012

2010

2009

2008

Wrote 15 papers:

DAC-2015-LiCSHLWY #hybrid #power management: A STT-RAM-based low-power hybrid register file for GPGPUs (GL, XC, GS, HH, YL, YW, HY), p. 6.
DATE-2015-LiLZGSSZCLY #energy #performance: An energy efficient backup scheme with low inrush current for nonvolatile SRAM in energy harvesting sensor nodes (HL, YL, QZ, YG, XS, GS, CZ, MFC, RL, HY), pp. 7–12.
DATE-2015-SunZLZZGSKRLZY #design #memory management: From device to system: cross-layer design exploration of racetrack memory (GS, CZ, HL, YZ, WZ, YG, YS, JOK, DR, YL, WZ, HY), pp. 1018–1023.
HPCA-2015-XieLWSW #coordination: Coordinated static and dynamic cache bypassing for GPUs (XX, YL, YW, GS, TW), pp. 76–88.
DAC-2014-ZhanXS #fine-grained #named: NoC-Sprinting: Interconnect for Fine-Grained Sprinting in the Dark Silicon Era (JZ, YX, GS), p. 6.
HPCA-2014-WangJXSX #adaptation #hybrid #migration #policy: Adaptive placement and migration policy for an STT-RAM-based hybrid cache (ZW, DAJ, CX, GS, YX), pp. 13–24.
HPCA-2014-ZhangPXSX #architecture #memory management #named: CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture (TZ, MP, CX, GS, YX), pp. 368–379.
DATE-2012-ChenSZX #3d #named #physics #synthesis: 3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs (YC, GS, QZ, YX), pp. 1185–1190.
DATE-2012-SunXX #design #memory management #modelling: Modeling and design exploration of FBDRAM as on-chip memory (GS, CX, YX), pp. 1507–1512.
DAC-2010-WuSDDXDL #3d #integration: Cost-driven 3D integration with interconnect layers (XW, GS, XD, RD, YX, CRD, JL), pp. 150–155.
DATE-2010-JooNDSCX #design #energy #memory management: Energy- and endurance-aware design of phase change memory caches (YJ, DN, XD, GS, NC, YX), pp. 136–141.
HPCA-2010-SunJCNXCL #architecture #energy #hybrid #performance: A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement (GS, YJ, YC, DN, YX, YC, HL), pp. 1–12.
HPCA-2009-SunDXLC #3d #architecture #novel: A novel architecture of the 3D stacked MRAM L2 cache for CMPs (GS, XD, YX, JL, YC), pp. 239–249.
DAC-2008-DongWSXLC #3d #architecture #evaluation #memory management #ram: Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement (XD, XW, GS, YX, HHL, YC), pp. 554–559.
DATE-2008-WangSX #framework #synthesis: A Variation Aware High Level Synthesis Framework (FW, GS, YX), pp. 1063–1068.