BibSLEIGH — Franco

Travelled to:

1 × Italy
1 × Switzerland
10 × Germany
6 × USA
8 × France

Collaborated with:

G.Pravadelli N.Bombieri G.Perbellini M.Poncino D.Quaglia D.Sciuto A.Fin S.Vinco S.Martini F.Ferrandi M.Turolla L.D.Guglielmo F.Ricciato E.Macii M.Monguzzi V.Guarnieri F.Stefanni G.D.Guglielmo A.Acquaviva V.Bertacco D.Chatterjee M.Becker W.Müller N.Roncolato N.Deganello P.Destro M.Serra H.Liu L.P.Carloni E.S.M.Ebeid E.Alessio R.Pietrangeli L.Gerli A.Balboni C.Costi M.Hampton F.Letombe N.Drago G.Ferrara M.Lora D.Trachanis J.Vanhese G.B.Defo T.Xie F.Mulas S.Carta G.Fenu P.Azzoni M.Bertoletti N.Dragone C.Guardiani W.Vendraminetto M.Loghi P.Gallo A.M.Kaushik H.D.Patel M.Borgatti A.Capello U.Rossi J.Lambert I.Moussa M.Petricca A.Sassone

Talks about:

simul (13) network (12) system (12) design (12) embed (11) model (9) verif (8) function (7) base (7) rtl (7)

Person: Franco Fummi

DBLP: Fummi:Franco

Contributed to:

2014

2013

2012

2010

2009

2008

2007

2006

2004

2005

2004

2003

2001

2000

1999

1998

1996

1994

Wrote 42 papers:

DATE-2014-FummiLSTVV #design #effectiveness #simulation: Moving from co-simulation to simulation for effective smart systems design (FF, ML, FS, DT, JV, SV), pp. 1–4.
DATE-2014-GuarnieriPSVBFMP #embedded #monitoring #verification: A cross-level verification methodology for digital IPs augmented with embedded timing monitors (VG, MP, AS, SV, NB, FF, EM, MP), pp. 1–6.
DAC-2013-BombieriLFC #c++ #synthesis: A method to abstract RTL IP blocks into C++ code and enable high-level synthesis (NB, HYL, FF, LPC), p. 9.
DATE-2013-BertaccoCBFVKP #on the #using: On the use of GP-GPUs for accelerating compute-intensive EDA applications (VB, DC, NB, FF, SV, AMK, HDP), pp. 1357–1366.
DAC-2012-VincoCBF #architecture #gpu #named: SAGA: SystemC acceleration on GPU architectures (SV, DC, VB, FF), pp. 115–120.
DATE-2012-BeckerDFMPV #embedded #evolution #modelling #named #scalability #verification: MOUSSE: Scaling modelling and verification to complex Heterogeneous Embedded Systems evolution (MB, GBD, FF, WM, GP, SV), pp. 296–299.
DATE-2012-BombieriFG #fault #framework #functional #named #simulation #verification: FAST-GP: An RTL functional verification framework based on fault simulation on GP-GPUs (NB, FF, VG), pp. 562–565.
DATE-2012-EbeidFQS #design #embedded #modelling #refinement #uml: Refinement of UML/MARTE models for the design of networked embedded systems (ESME, FF, DQ, FS), pp. 1072–1077.
DATE-2012-GuglielmoGFP #design #embedded #modelling #verification: Enabling dynamic assertion-based verification of embedded software through model-driven design (GDG, LDG, FF, GP), pp. 212–217.
DAC-2010-BombieriFP #abstraction #embedded: Abstraction of RTL IPs into embedded software (NB, FF, GP), pp. 24–29.
DATE-2010-BeckerGF0PX #design #refinement: RTOS-aware refinement for TLM2.0-based HW/SW designs (MB, GDG, FF, WM, GP, TX), pp. 1053–1058.
DATE-2010-GuglielmoFP #analysis: Vacuity analysis for property qualification by mutation of checkers (LDG, FF, GP), pp. 478–483.
SAC-2010-MulasACFQF #adaptation #energy #network: Network-adaptive management of computation energy in wireless sensor networks (FM, AA, SC, GF, DQ, FF), pp. 756–763.
DATE-2009-BombieriFPHL #functional #verification: Functional qualification of TLM verification (NB, FF, GP, MH, FL), pp. 190–195.
DATE-2009-BombieriFPV #generative: Correct-by-construction generation of device drivers based on RTL testbenches (NB, FF, GP, SV), pp. 1500–1505.
DATE-2009-FummiPQA #energy #flexibility #network #simulation: Flexible energy-aware simulation of heterogenous wireless sensor networks (FF, GP, DQ, AA), pp. 1638–1643.
DATE-2009-FummiPR #design #embedded #middleware: Networked embedded system applications design driven by an abstract middleware environment (FF, GP, NR), pp. 1024–1029.
DATE-2008-BombieriDF #automation #design #generative: Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation (NB, ND, FF), pp. 15–20.
DATE-2008-BombieriFP #communication #interface: A Mutation Model for the SystemC TLM 2.0 Communication Interfaces (NB, FF, GP), pp. 396–401.
DATE-2007-AlessioFQT #design #embedded #modelling #simulation: Modeling and simulation alternatives for the design of networked embedded systems (EA, FF, DQ, MT), pp. 1030–1035.
DATE-2007-AzzoniBDFGV #optimisation: Yield-aware placement optimization (PA, MB, ND, FF, CG, WV), pp. 1232–1237.
DATE-2007-BombieriFP #design #functional #incremental #refinement #validation: Incremental ABV for functional validation of TL-to-RTL design refinement (NB, FF, GP), pp. 882–887.
DATE-2007-DestroFP #refinement #thread: A smooth refinement flow for co-designing HW and SW threads (PD, FF, GP), pp. 105–110.
DATE-2007-FummiPPQ #design #embedded #interactive #middleware: Interactive presentation: A middleware-centric design flow for networked embedded systems (FF, GP, RP, DQ), pp. 1048–1053.
DATE-2006-BombieriFP #evaluation #on the #reuse #verification: On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL (NB, FF, GP), pp. 1007–1012.
DATE-DF-2006-FummiQRT #mobile #modelling #network #simulation: Modeling and simulation of mobile gateways interacting with wireless sensor networks (FF, DQ, FR, MT), pp. 106–111.
SFM-2006-BombieriFP #design #hardware #simulation #verification: Hardware Design and Simulation for Verification (NB, FF, GP), pp. 1–29.
DATE-2005-BorgattiCRLMFP04 #configuration management #design #multi #verification: An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems (MB, AC, UR, JLL, IM, FF, GP), pp. 266–271.
DATE-2005-FummiLMMPP #hardware #prototype: Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation (FF, ML, SM, MM, GP, MP), pp. 798–803.
DATE-DF-2004-FummiMMPP #analysis #architecture #industrial #modelling #network: Modeling and Analysis of Heterogeneous Industrial Networks Architectures (FF, SM, MM, GP, MP), pp. 342–344.
DATE-DF-2004-FummiMPPRT #embedded: Heterogeneous Co-Simulation of Networked Embedded Systems (FF, SM, GP, MP, FR, MT), pp. 168–173.
DATE-v1-2004-FummiMPP #integration #multi: Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC (FF, SM, GP, MP), pp. 564–569.
DAC-2003-FummiPGPMR #embedded #modelling #simulation: A timing-accurate modeling and simulation environment for networked embedded systems (FF, GP, PG, MP, SM, FR), pp. 42–47.
DATE-2003-DragoFMPP #architecture #embedded #estimation #performance #tuple: Estimation of Bus Performance for a Tuplespace in an Embedded Architecture (ND, FF, MM, GP, MP), pp. 20188–20195.
DATE-2001-FerrandiFSFF #behaviour #functional #generative #modelling #testing: Functional test generation for behaviorally sequential models (FF, GF, DS, AF, FF), pp. 403–410.
DAC-2000-FinF #analysis #simulation: A Web-CAD methodology for IP-core analysis and simulation (AF, FF), pp. 597–600.
DATE-2000-FinF #fault #functional #generative #testing: A VHDL Error Simulator for Functional Test Generation (AF, FF), pp. 390–395.
DATE-1999-FerrandiFGS #functional #generative #specification: Symbolic Functional Vector Generation for VHDL Specifications (FF, FF, LG, DS), p. 442–?.
DATE-1998-FerrandiFMP #behaviour #estimation: Power Estimation of Behavioral Descriptions (FF, FF, EM, MP), pp. 762–766.
DAC-1996-FerrandiFMPS #automaton #network #optimisation: Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques (FF, FF, EM, MP, DS), pp. 467–470.
EDAC-1994-BalboniCFS #architecture #array #behaviour: From Behavioral Description to Systolic Array Based Architectures (AB, CC, FF, DS), p. 657.
EDAC-1994-FummiSS #approach #fault #functional #generative #testing: A Functional Approach to Delay Faults Test Generation for Sequential Circuits (FF, DS, MS), pp. 51–57.