BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × France
2 × USA
Collaborated with:
A.Adir A.Nahir A.Ziv G.Shurek J.Schumann S.Copty S.Landa D.Goodman D.Hershcovich O.Hershkovitz B.G.Hickerson K.Holtz W.Kadry A.Koyfman J.M.Ludden R.R.Pratt M.Schiffli B.S.Onge B.W.Thompto E.Tsanko
Talks about:
silicon (4) verif (3) valid (2) power (2) post (2) pre (2) methodolog (1) processor (1) transact (1) resourc (1)

Person: Charles Meissner

DBLP DBLP: Meissner:Charles

Contributed to:

DAC 20142014
DAC 20112011
DATE 20112011

Wrote 3 papers:

DAC-2014-AdirGHHHHKKLMNPSOTTZ #memory management #transaction #verification
Verification of Transactional Memory in POWER8 (AA, DG, DH, OH, BGH, KH, WK, AK, JML, CM, AN, RRP, MS, BSO, BWT, ET, AZ), p. 6.
DAC-2011-AdirNSZMS #validation #verification
Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor (AA, AN, GS, AZ, CM, JS), pp. 569–574.
DATE-2011-AdirCLNSZMS #validation #verification
A unified methodology for pre-silicon verification and post-silicon validation (AA, SC, SL, AN, GS, AZ, CM, JS), pp. 1590–1595.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.