Travelled to:3 × USA
Collaborated with:L.Fournier M.Levinger A.Ziv D.Chatterjee R.Morad V.Bertacco A.Adir D.Goodman D.Hershcovich O.Hershkovitz B.G.Hickerson K.Holtz W.Kadry J.M.Ludden C.Meissner A.Nahir R.R.Pratt M.Schiffli B.S.Onge B.W.Thompto E.Tsanko
Talks about:architectur (3) instruct (2) power (2) applicaiton (1) transact (1) platform (1) develop (1) acceler (1) output (1) memori (1)
Person: Anatoly Koyfman
DBLP: Koyfman:Anatoly
Contributed to:
201420121999Wrote 3 papers:
- DAC-2014-AdirGHHHHKKLMNPSOTTZ #memory management #transaction #verification
- Verification of Transactional Memory in POWER8 (AA, DG, DH, OH, BGH, KH, WK, AK, JML, CM, AN, RRP, MS, BSO, BWT, ET, AZ), p. 6.
- DAC-2012-ChatterjeeKMZB #architecture #platform
- Checking architectural outputs instruction-by-instruction on acceleration platforms (DC, AK, RM, AZ, VB), pp. 955–961.
- DAC-1999-FournierKL #architecture #validation
- Developing an Architecture Validation Suite: Applicaiton to the PowerPC Architecture (LF, AK, ML), pp. 189–194.