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Travelled to:
5 × USA
Collaborated with:
Y.I.Ismail N.Menezes C.V.Kashyap F.Dartu K.Killpack P.Mukherjee P.Li M.H.Chowdhury S.Mei E.Chiprout U.Choudhury N.Hakim
Talks about:
circuit (3) model (3) approxim (2) effect (2) time (2) rlck (2) cell (2) properti (1) statist (1) respons (1)

Person: Chirayu S. Amin

DBLP DBLP: Amin:Chirayu_S=

Contributed to:

DAC 20142014
DAC 20082008
DAC 20062006
DAC 20052005
DAC 20032003

Wrote 7 papers:

DAC-2014-MukherjeeAL #approximate
Approximate property checking of mixed-signal circuits (PM, CSA, PL), p. 6.
DAC-2008-MenezesKA #grid #power management #verification
A “true” electrical cell model for timing, noise, and power grid verification (NM, CVK, CSA), pp. 462–467.
DAC-2006-AminKMKC #library #multi
A multi-port current source model for multiple-input switching effects in CMOS library cells (CSA, CVK, NM, KK, EC), pp. 247–252.
DAC-2005-AminID #approximate #using
Piece-wise approximations of RLCK circuit responses using moment matching (CSA, YII, FD), pp. 927–932.
DAC-2005-AminMKDCHI #analysis #how #question #statistics
Statistical static timing analysis: how simple can we get? (CSA, NM, KK, FD, UC, NH, YII), pp. 652–657.
Realizable RLCK circuit crunching (CSA, MHC, YII), pp. 226–231.
DAC-2003-MeiAI #order #performance #reduction
Efficient model order reduction including skin effect (SM, CSA, YII), pp. 232–237.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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