BibSLEIGH corpus
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Open Knowledge
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Travelled to:
6 × USA
Collaborated with:
B.Krauter N.Menezes C.S.Amin K.Killpack E.Chiprout F.Liu S.V.Kumar S.S.Sapatnekar C.J.Alpert A.Devgan H.Su D.Widiger
Talks about:
nois (4) model (3) analysi (2) effect (2) time (2) cell (2) interconnect (1) speedpath (1) framework (1) distribut (1)

Person: Chandramouli V. Kashyap

DBLP DBLP: Kashyap:Chandramouli_V=

Contributed to:

DAC 20082008
DAC 20072007
DAC 20062006
DAC 20052005
DAC 20032003
DAC 20002000

Wrote 7 papers:

DAC-2008-KumarKS #analysis #framework
A framework for block-based timing sensitivity analysis (SVK, CVK, SSS), pp. 688–693.
DAC-2008-MenezesKA #grid #power management #verification
A “true” electrical cell model for timing, noise, and power grid verification (NM, CVK, CSA), pp. 462–467.
DAC-2007-KillpackKC #feedback #metric
Silicon Speedpath Measurement and Feedback into EDA flows (KK, CVK, EC), pp. 390–395.
DAC-2006-AminKMKC #library #multi
A multi-port current source model for multiple-input switching effects in CMOS library cells (CSA, CVK, NM, KK, EC), pp. 247–252.
DAC-2005-SuWKLK #analysis #effectiveness #embedded #functional #performance
A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis (HS, DW, CVK, FL, BK), pp. 186–189.
DAC-2003-AlpertLKD #metric #using
Delay and slew metrics using the lognormal distribution (CJA, FL, CVK, AD), pp. 382–385.
A realizable driving point model for on-chip interconnect with inductance (CVK, BK), pp. 190–195.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.