BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
6 × USA
Collaborated with:
Q.Wu P.Juang M.Martonosi K.Skadron D.Bhandarkar A.Pyatakov A.Spiridonov E.Raman D.I.August
Talks about:
processor (2) frequenc (2) perform (2) multipl (2) control (2) voltag (2) memori (2) domain (2) clock (2) microprocessor (1)

Person: Douglas W. Clark

DBLP DBLP: Clark:Douglas_W=

Facilitated 1 volumes:


Contributed to:

HPCA 20052005
ASPLOS 20042004
CGO 20042004
HPCA 19971997
ASPLOS 19911991
ASPLOS 19871987

Wrote 6 papers:

HPCA-2005-WuJMC #adaptation #multi
Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors (QW, PJ, MM, DWC), pp. 178–189.
ASPLOS-2004-WuJMC #multi #online
Formal online methods for voltage/frequency control in multiple clock domain microprocessors (QW, PJ, MM, DWC), pp. 248–259.
CGO-2004-WuPSRCA #memory management #profiling #using
Exposing Memory Access Regularities Using Object-Relative Memory Profiling (QW, AP, AS, ER, DWC, DIA), pp. 315–324.
HPCA-1997-SkadronC #design #trade-off
Design Issues and Tradeoffs for Write Buffers (KS, DWC), pp. 144–155.
ASPLOS-1991-BhandarkarC #architecture #hardware #performance
Performance From Architecture: Comparing a RISC and CISC with Similar Hardware Organization (DB, DWC), pp. 310–319.
ASPLOS-1987-Clark #performance #pipes and filters
Pipelining and Performance in the VAX 8800 Processor (DWC), pp. 173–177.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.