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Travelled to:
1 × Germany
2 × France
8 × USA
Collaborated with:
C.Bellon H.Krupnova K.Sakouti F.Poirot R.Leveugle D.R.Brasen D.Jacquet E.F.M.Kouka G.Thuau P.Basset A.Abbara C.Safinia M.Crastes C.Duff J.M.Gobbi P.Abouzeid T.Michel R.Doucet P.Chapier V.Gerousis O.Levia P.G.Paulin M.Pinto C.Rowen L.Ghanmi A.Ghrab M.Hamdoun B.Missaoui K.Skiba A.Liothin S.Sadier R.Velazco F.Grillot M.Issenman
Talks about:
design (4) base (4) partit (3) method (3) test (3) advantag (2) perfect (2) circuit (2) analysi (2) neural (2)

Person: Gabriele Saucier

DBLP DBLP: Saucier:Gabriele

Contributed to:

DATE 20022002
DATE 19991999
DAC 19971997
DAC 19911991
DAC 19901990
DAC 19891989
DAC 19871987
DAC 19851985
DAC 19841984
DAC 19821982
DAC 19811981

Wrote 17 papers:

DATE-2002-GerousisLPPRS #framework #platform #question
Who Owns the Platform? (VG, OL, PGP, MP, CR, GS), p. 238.
DATE-2002-GhanmiGHMSS #paradigm #reuse
E-Design Based on the Reuse Paradigm (LG, AG, MH, BM, KS, GS), pp. 214–220.
DATE-1999-KrupnovaS #clustering #multi
Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs (HK, GS), p. 587–?.
DAC-1997-KrupnovaAS #clustering
A Hierarchy-Driven FPGA Partitioning Method (HK, AA, GS), pp. 522–525.
EDAC-1994-BrasenS #clustering
FPGA Partitioning for Critical Paths (DRB, GS), pp. 99–103.
EDAC-1994-MichelLSDC #dependence
Taking Advantage of ASICs to Improve Dependability with Very Low Overheads (TM, RL, GS, RD, PC), pp. 14–18.
EDAC-1994-SafiniaLS #analysis #functional #modelling
Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling (CS, RL, GS), pp. 349–353.
EDAC-1994-Saucier #design #network #recognition
Design of a Digital Neural Chip: Application to Optical Character Recognition by Neural Network (DJ, GS), pp. 256–260.
A Technology Mapping Method Based On Perfect And Semi-Perfect Matchings (MC, KS, GS), pp. 93–98.
DAC-1990-AbouzeidSSP #multi #synthesis
Multilevel Synthesis Minimizing the Routing Factor (PA, KS, GS, FP), pp. 365–368.
DAC-1989-SaucierDP #using
State Assignment Using a New Embedding Method Based on an Intersecting Cube Theory (GS, CD, FP), pp. 321–326.
DAC-1987-KoukaS #data analysis #design
An Application of Exploratory Data Analysis Techniques to Floorplan Design (EFMK, GS), pp. 654–658.
DAC-1985-SaucierT #layout
Systematic and optimized layout of MOS cells (GS, GT), pp. 53–61.
DAC-1984-SaucierB #control flow #using
VLSI test expertise system using a control flow model (GS, CB), pp. 497–503.
DAC-1982-BassetS #design #testing #top-down
Top down design and testability of VLSI circuits (PB, GS), pp. 851–857.
DAC-1982-BellonLSSVGI #automation #generative #source code
Automatic generation of microprocessor test programs (CB, AL, SS, GS, RV, FG, MI), pp. 566–573.
DAC-1981-BellonSG #hardware
Hardware description levels and test for complex circuits (CB, GS, JMG), pp. 213–219.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.