Travelled to:1 × Germany
2 × USA
5 × France
Collaborated with:∅ A.Ammari G.Saucier P.Maistri Y.Monnet M.Renaudin C.Safinia A.Calvez P.Vanhauwaert A.Papadimitriou D.Hély V.Beroulle T.Michel R.Doucet P.Chapier V.Maingot E.Teyssou P.Moitrel C.Mourtel N.Feyt J.Rigaud A.Tria
Talks about:fault (8) inject (3) model (3) advantag (2) circuit (2) toler (2) level (2) laser (2) evalu (2) time (2)
Person: Régis Leveugle
DBLP: Leveugle:R=eacute=gis
Contributed to:
201420092007
20052004200219941993Wrote 9 papers:
- DATE-2014-PapadimitriouHBML #clustering #fault #injection #modelling #multi #towards
- A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks (AP, DH, VB, PM, RL), pp. 1–4.
- DATE-2009-LeveugleCMV #fault #injection #quantifier #statistics
- Statistical fault injection: Quantified error and confidence (RL, AC, PM, PV), pp. 502–506.
- DATE-2007-LeveugleAMTMMFRT #evaluation #fault #modelling
- Experimental evaluation of protections against laser-induced faults and consequences on fault modeling (RL, AA, VM, ET, PM, CM, NF, JBR, AT), pp. 1587–1592.
- DAC-2005-MonnetRL #evaluation #fault
- Asynchronous circuits transient faults sensitivity evaluation (YM, MR, RL), pp. 863–868.
- DATE-v1-2004-LeveugleA #fault #injection
- Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow (RL, AA), pp. 590–595.
- DATE-2002-Leveugle #automation #detection #fault
- Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance (RL), pp. 837–841.
- EDAC-1994-MichelLSDC #dependence
- Taking Advantage of ASICs to Improve Dependability with Very Low Overheads (TM, RL, GS, RD, PC), pp. 14–18.
- EDAC-1994-SafiniaLS #analysis #functional #modelling
- Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling (CS, RL, GS), pp. 349–353.
- DAC-1993-Leveugle #fault tolerance
- Optimized State Assignment of single fault Tolerant FSMs Based on SEC Codes (RL), pp. 14–18.