Travelled to:
7 × USA
Collaborated with:
Y.Chang H.Chang Y.Yu C.Chiang Y.Yang K.H.Tam J.Jou G.Lin L.Chang H.Hung Y.Chan S.Sinha
Talks about:
use (4) critic (3) spare (3) time (3) gate (3) cell (3) base (3) eco (3) simultan (2) function (2)
Person: Iris Hui-Ru Jiang
DBLP: Jiang:Iris_Hui=Ru
Contributed to:
Wrote 8 papers:
- DAC-2015-YangTJ #analysis
- Criticality-dependency-aware timing characterization and analysis (YMY, KHT, IHRJ), p. 6.
- DAC-2014-ChangJC #configuration management #functional #using
- Functional ECO Using Metal-Configurable Gate-Array Spare Cells (HYC, IHRJ, YWC), p. 6.
- DAC-2013-YuLJC #classification #detection #feature model #using
- Machine-learning-based hotspot detection using topological classification and critical feature extraction (YTY, GHL, IHRJ, CC), p. 6.
- DAC-2012-ChangJC #configuration management #optimisation #using
- Timing ECO optimization using metal-configurable gate-array spare cells (HYC, IHRJ, YWC), pp. 802–807.
- DAC-2012-YuCSJC #design #detection #using
- Accurate process-hotspot detection using critical design rule extraction (YTY, YCC, SS, IHRJ, CC), pp. 1167–1172.
- DAC-2011-ChangJC #functional
- Simultaneous functional and timing ECO (HYC, IHRJ, YWC), pp. 140–145.
- DAC-2009-JiangCCH #design #low cost
- Matching-based minimum-cost spare cell selection for design changes (IHRJ, HYC, LGC, HBH), pp. 408–411.
- DAC-1999-JiangJC #optimisation #performance
- Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation (IHRJ, JYJ, YWC), pp. 90–95.