Travelled to:1 × USA
3 × France
3 × Germany
Collaborated with:J.L.Rosselló S.A.Bota B.Alorda G.Torrens S.Bhunia K.Roy S.Barcelo X.Gili C.d.Benito M.Rosales V.Canals A.Keshavarzi
Talks about:model (4) delay (4) base (3) crosstalk (2) thermal (2) compact (2) stabil (2) resist (2) critic (2) power (2)
Person: Jaume Segura
DBLP: Segura:Jaume
Contributed to:
201120102007200620052004
2002Wrote 9 papers:
- DATE-2011-AlordaTBS #embedded #optimisation #using
- Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation (BA, GT, SAB, JS), pp. 986–991.
- DATE-2011-BarceloGBS #estimation #performance #scalability
- An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computation (SB, XG, SAB, JS), pp. 1602–1607.
- DATE-2010-AlordaTBS #power management
- Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs (BA, GT, SAB, JS), pp. 429–434.
- DATE-2007-RosselloBBS #statistics #testing
- Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs (JLR, CdB, SAB, JS), pp. 1271–1276.
- DATE-2006-RosselloS #fault #identification
- A compact model to identify delay faults due to crosstalk (JLR, JS), pp. 902–906.
- DATE-2005-BotaRRS #testing
- Smart Temperature Sensor for Thermal Testing of Cell-Based ICs (SAB, MR, JLR, JS), pp. 464–465.
- DATE-2005-RosselloCBKS #concurrent #performance
- A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs (JLR, VC, SAB, AK, JS), pp. 206–211.
- DATE-v2-2004-RosselloS
- A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk (JLR, JS), pp. 954–961.
- DAC-2002-BhuniaRS #analysis #detection #fault #locality #novel
- A novel wavelet transform based transient current analysis for fault detection and localization (SB, KR, JS), pp. 361–366.