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Travelled to:
1 × France
1 × Germany
3 × USA
Collaborated with:
I.Verbauwhede D.D.Hwang A.Hodjat B.Lai S.Yang P.Schaumont M.Badaroglu S.Donnay P.Wambacq H.D.Man G.G.E.Gielen
Talks about:
channel (4) side (4) design (3) circuit (2) resist (2) attack (2) secur (2) logic (2) cmos (2) cryptograph (1)

Person: Kris Tiri

DBLP DBLP: Tiri:Kris

Contributed to:

DAC 20072007
DAC 20052005
DATE 20052005
DATE v1 20042004
DAC 20022002

Wrote 7 papers:

Side-Channel Attack Pitfalls (KT), pp. 15–20.
DAC-2005-TiriHHLYSV #embedded #encryption
A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing (KT, DDH, AH, BCL, SY, PS, IV), pp. 222–227.
DAC-2005-TiriV #modelling #simulation
Simulation models for side-channel information leaks (KT, IV), pp. 228–233.
DATE-2005-TiriV #constant #design #difference #logic #power management
Design Method for Constant Power Consumption of Differential Logic Circuits (KT, IV), pp. 628–633.
DATE-2005-TiriV05a #design
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs (KT, IV), pp. 58–63.
DATE-v1-2004-TiriV #design #implementation #logic
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation (KT, IV), pp. 246–251.
DAC-2002-BadarogluTDWMVG #optimisation #reduction #using
Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients (MB, KT, SD, PW, HDM, IV, GGEG), pp. 399–404.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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