BibSLEIGH — Hugo_De

Travelled to:

12 × USA
3 × Germany
5 × France

Collaborated with:

F.Catthoor G.Goossens L.J.M.Claesen B.Lin ∅ D.Verkest S.Donnay W.Geurts P.Six P.Wambacq G.G.E.Gielen S.Vercauteren M.Badaroglu M.Miranda I.Bolsens G.G.d.Jong S.Note F.Thoen C.Ykman-Couvreur D.Desmet K.Schoofs J.Vandewalle P.Odent S.Perremans R.Lauwereins K.Croes G.V.d.Plas G.Vandersteen M.Engels F.Vermeulen M.Kaspar M.Cornero F.Depuydt P.Vanbekbergen H.Cai W.D.Rammelaere J.M.Rabaey B.Mei S.Vernalde C.Kulkarni C.Ghez J.V.D.Steen E.Verlind T.Kolks F.H.M.Franssen L.Nachtergaele H.Samsom I.Vandeweerd L.Rijnders W.Eberle H.Ziad K.Tiri I.Verbauwhede P.Dobrovolný S.Rawat W.H.J.Jr. J.A.Darringer D.Gajski P.O.Pistilli C.Harris J.Solomon M.v.Heijningen V.Gravot C.Wong P.Marchal P.Yang A.S.Prayati N.Cossement J.L.d.S.Jr. S.Wuytack

Talks about:

system (9) applic (7) time (7) high (7) architectur (6) optim (6) generat (5) circuit (5) simul (5) level (5)

Person: Hugo De Man

DBLP: Man:Hugo_De

Contributed to:

2004

2003

2002

2001

2000

1999

1998

1997

1996

1995

1994

1992

1991

1990

1989

1986

Wrote 34 papers:

DAC-2004-PlasBVDWDGM #simulation: High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects (GVdP, MB, GV, PD, PW, SD, GGEG, HDM), pp. 854–859.
DAC-2004-RawatJJDGPMHS: Were the good old days all that good?: EDA then and now (SR, WHJJ, JAD, DG, POP, HDM, CH, JS), p. 543.
DATE-v1-2004-BadarogluWPDGM #reduction: Digital Ground Bounce Reduction by Phase Modulation of the Clock (MB, PW, GVdP, SD, GGEG, HDM), pp. 88–93.
DATE-2003-EberleVWDGM #automation #behaviour #modelling #simulation: Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver (WE, GV, PW, SD, GGEG, HDM), pp. 10642–10649.
DATE-2003-MeiVVML #architecture #configuration management #parallel #scheduling #using: Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling (BM, SV, DV, HDM, RL), pp. 10296–10301.
DAC-2002-BadarogluTDWMVG #optimisation #reduction #using: Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients (MB, KT, SD, PW, HDM, IV, GGEG), pp. 399–404.
DATE-2002-Man #complexity #integration #on the: On Nanoscale Integration and Gigascale Complexity in the Post.Com World (HDM), p. 12.
DATE-2001-BadarogluHGDMGEB #generative #multi #scalability #simulation: High-level simulation of substrate noise generation from large digital circuits with multiple supplies (MB, MvH, VG, SD, HDM, GGEG, ME, IB), pp. 326–330.
DATE-2001-KulkarniGMCM #embedded #layout #multi: Cache conscious data layout organization for embedded multimedia applications (CK, CG, MM, FC, HDM), pp. 686–693.
DATE-2001-WongMYCMPCLV #concurrent #summary: Task concurrency management methodology summary (CW, PM, PY, FC, HDM, ASP, NC, RL, DV), p. 813.
DAC-2000-DesmetVM #generative #operating system: Operating system based software generation for systems-on-chip (DD, DV, HDM), pp. 396–401.
DATE-2000-VermeulenCMV #embedded #reuse: Formalized Three-Layer System-Level Reuse Model and Methodology for Embedded Data-Dominated Applications (FV, FC, HDM, DV), pp. 92–98.
DATE-1999-WambacqDZEMB: A Single-Package Solution for Wireless Transceivers (PW, SD, HZ, ME, HDM, IB), p. 425–?.
DAC-1998-SilvaYMCWJCVSM #data transfer #performance #synthesis: Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer (JLdSJ, CYC, MM, KC, SW, GGdJ, FC, DV, PS, HDM), pp. 76–81.
DAC-1997-Man #education #question: Education for the Deep Submicron Age: Business as Usual? (HDM), pp. 307–312.
EDTC-1997-MirandaKCM #architecture #generative #hardware #optimisation: Architectural exploration and optimization for counter based hardware address generation (MM, MK, FC, HDM), pp. 293–298.
EDTC-1997-ThoenSJGM #embedded #graph #multi #realtime #synthesis #thread: Multi-thread graph: a system model for real-time embedded software synthesis (FT, JVDS, GGdJ, GG, HDM), pp. 476–481.
DAC-1996-VercauterenLM #architecture #embedded: Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications (SV, BL, HDM), pp. 521–526.
DAC-1996-VercauterenLM96a #architecture #embedded #kernel #realtime: A Strategy for Real-Time Kernel Support in Application-Specific HW/SW Embedded Architectures (SV, BL, HDM), pp. 678–683.
LCT-RTS-1995-ThoenCGM #information management #realtime #synthesis: Software Synthesis for Real-Time Information Processing Systems (FT, MC, GG, HDM), pp. 60–69.
DAC-1994-VerlindKJLM #abstraction #communication #performance #verification: A Time Abstraction Method for Efficient Verification of Communicating Systems (EV, TK, GGdJ, BL, HDM), pp. 609–614.
EDAC-1994-DepuydtGGM #graph #optimisation #pipes and filters #scheduling: Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization (FD, WG, GG, HDM), pp. 490–494.
EDAC-1994-FranssenNSCM #control flow #optimisation #performance #simulation: Control flow optimization for fast system simulation and storage minimization (FHMF, LN, HS, FC, HDM), pp. 20–24.
EDAC-1994-SchoofsGM #architecture #design #multi #optimisation: Signal Type Optimisation in the Design of Time-Multiplexed DSP Architectures (KS, GG, HDM), pp. 502–506.
EDAC-1994-VanbekbergenYLM #graph #interface #specification: A Generalized Signal Transition Graph Model for Specification of Complex Interfaces (PV, CYC, BL, HDM), pp. 378–384.
DAC-1992-GeurtsCM #throughput: Time Constrained Allocation and Assignment Techniques for High Throughput Signal Processing (WG, FC, HDM), pp. 124–127.
DAC-1991-NoteGCM #architecture #named #synthesis #throughput: Cathedral-III: Architecture-Driven High-level Synthesis for High Throughput DSP Applications (SN, WG, FC, HDM), pp. 597–602.
DAC-1990-CaiNSM #assembly #layout #performance: A Data Path Layout Assembler for High Performance DSP Circuits (HC, SN, PS, HDM), pp. 306–311.
DAC-1989-BolsensRCM #analysis #behaviour #debugging #logic: Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour (IB, WDR, LJMC, HDM), pp. 513–518.
DAC-1989-GoossensVM #optimisation #scheduling: Loop Optimization in Register-Transfer Scheduling for DSP-Systems (GG, JV, HDM), pp. 826–831.
DAC-1989-OdentCM #feedback #implementation #multi #scalability: Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator (PO, LJMC, HDM), pp. 25–30.
DAC-1989-PerremansCM #analysis: Static Timing Analysis of Dynamically Sensitizable Paths (SP, LJMC, HDM), pp. 568–573.
DAC-1989-VandweerdCRSM #automation #generative #named: REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures (IV, KC, LR, PS, HDM), pp. 694–697.
DAC-1986-SixCRM #generative: An intelligent module generator environment (PS, LJMC, JMR, HDM), pp. 730–735.