BibSLEIGH — Ingrid

Travelled to:

5 × France
6 × Germany
8 × USA

Collaborated with:

P.Schaumont K.Tiri V.Rozic A.V.Herrewege J.Fan R.d.Clercq J.Delvaux B.Yang W.Dehaene K.Sakiyama F.Veljkovic J.Balasch B.Preneel S.K.Shukla H.Kuo C.J.Scheers J.M.Rabaey D.D.Hwang A.Hodjat B.Lai S.Yang S.S.Roy F.Vercauteren L.Uhsadel O.Reparaz A.Das Ü.Koçabas A.Sadeghi D.Karaklajic J.Schmidt L.Batina B.C.Lai W.Qin C.Piguet B.Kienhuis K.Keutzer M.Sarrafzadeh N.Mentens O.Villa M.Monchiero G.Palermo M.Badaroglu S.Donnay P.Wambacq H.D.Man G.G.E.Gielen Y.Fan

Talks about:

design (12) secur (7) embed (5) implement (4) test (4) base (4) low (4) generat (3) channel (3) random (3)

Person: Ingrid Verbauwhede

DBLP: Verbauwhede:Ingrid

Contributed to:

2015

2014

2013

2012

2011

2010

2008

2007

2006

2005

2004

2003

2002

2001

1994

Wrote 28 papers:

DAC-2015-RozicYDV #generative #performance #random: Highly efficient entropy extraction for true random number generators on FPGAs (VR, BY, WD, IV), p. 6.
DATE-2015-ClercqRVV #encryption #implementation #performance: Efficient software implementation of ring-LWE encryption (RdC, SSR, FV, IV), pp. 339–344.
DATE-2015-YangRMDV #embedded #framework #generative #on the fly #platform #random #testing: Embedded HW/SW platform for on-the-fly testing of true random number generators (BY, VR, NM, WD, IV), pp. 345–350.
DAC-2014-ClercqUHV #implementation #power management: Ultra Low-Power implementation of ECC on the ARM Cortex-M0+ (RdC, LU, AVH, IV), p. 6.
DAC-2014-HerrewegeV: Software Only, Extremely Compact, Keccak-based Secure PRNG on ARM Cortex-M (AVH, IV), p. 6.
DATE-2014-DelvauxV: Key-recovery attacks on various RO PUF constructions via helper data manipulation (JD, IV), pp. 1–6.
DAC-2013-FanRRV #design #encryption #energy #security: Low-energy encryption for medical devices: security adds an extra design dimension (JF, OR, VR, IV), p. 6.
DATE-2012-DasKSV #design #encryption #testing: PUF-based secure test wrapper design for cryptographic SoC testing (AD, ÜK, ARS, IV), pp. 866–869.
DATE-2012-VeljkovicRV #generative #implementation #low cost #on the fly #random #testing: Low-cost implementations of on-the-fly tests for random number generators (FV, VR, IV), pp. 959–964.
DATE-2011-KaraklajicFSV #detection #fault #low cost #using: Low-cost fault detection method for ECC using Montgomery powering ladder (DK, JF, JMS, IV), pp. 1016–1021.
DATE-2010-BalaschVP #embedded #framework #privacy: An embedded platform for privacy-friendly road charging applications (JB, IV, BP), pp. 867–872.
DATE-2008-FanBSV #algebra #design #encryption: FPGA Design for Algebraic Tori-Based Public-Key Cryptography (JF, LB, KS, IV), pp. 1292–1297.
DATE-2007-VerbauwhedeS #design #security #trust: Design methods for security and trust (IV, PS), pp. 672–677.
DATE-2006-SchaumontSV #design #hardware #semantics: Design with race-free hardware semantics (PS, SKS, IV), pp. 571–576.
DAC-2005-SchaumontLQV #architecture #design #energy #multi #thread: Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design (PS, BCCL, WQ, IV), pp. 27–30.
DAC-2005-TiriHHLYSV #embedded #encryption: A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing (KT, DDH, AH, BCL, SY, PS, IV), pp. 222–227.
DAC-2005-TiriV #modelling #simulation: Simulation models for side-channel information leaks (KT, IV), pp. 228–233.
DATE-2005-TiriV #constant #design #difference #logic #power management: Design Method for Constant Power Consumption of Differential Logic Circuits (KT, IV), pp. 628–633.
DATE-2005-TiriV05a #design: A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs (KT, IV), pp. 58–63.
DATE-2005-VillaSVMP #framework #integration #memory management #multi #performance: Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip (OV, PS, IV, MM, GP), pp. 804–805.
DATE-v1-2004-SchaumontV #interactive #partial evaluation: Interactive Cosimulation with Partial Evaluation (PS, IV), pp. 642–647.
DATE-v1-2004-TiriV #design #implementation #logic: A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation (KT, IV), pp. 246–251.
DATE-v2-2004-VerbauwhedeSPK #architecture #design #embedded #energy #multi #performance: Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing (IV, PS, CP, BK), pp. 988–995.
DAC-2003-HwangLSSFYHV #design #embedded: Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system (DDH, BCL, PS, KS, YF, SY, AH, IV), pp. 60–65.
DAC-2002-BadarogluTDWMVG #optimisation #reduction #using: Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients (MB, KT, SD, PW, HDM, IV, GGEG), pp. 399–404.
DAC-2002-SchaumontKV #design: Unlocking the design secrets of a 2.29 Gb/s Rijndael processor (PS, HK, IV), pp. 634–639.
DAC-2001-SchaumontVKS #configuration management: A Quick Safari Through the Reconfiguration Jungle (PS, IV, KK, MS), pp. 172–177.
DAC-1994-VerbauwhedeSR #estimation #memory management #synthesis: Memory Estimation for High Level Synthesis (IV, CJS, JMR), pp. 143–148.