BibSLEIGH — Patrick

Travelled to:

6 × Germany
7 × USA
9 × France

Collaborated with:

I.Verbauwhede S.Vernalde X.Guo M.Engels I.Bolsens Z.Chen R.Cmar L.Rijnders H.Eldib C.Wang N.F.Ghalaty A.Aysu S.K.Shukla H.Kuo R.Pasko D.D.Hwang A.Hodjat B.Lai S.Yang M.M.I.Taha A.Sinha B.C.Lai W.Qin C.Piguet B.Kienhuis K.Keutzer M.Sarrafzadeh O.Villa M.Monchiero G.Palermo C.K.Lennard G.G.d.Jong A.Haverinen P.Hardee M.Srivastav S.Huang D.Ganta M.B.Henry L.Nazhandali K.Tiri K.Sakiyama Y.Fan

Talks about:

design (11) system (5) softwar (3) channel (3) embed (3) side (3) base (3) asic (3) multiprocessor (2) architectur (2)

Person: Patrick Schaumont

DBLP: Schaumont:Patrick

Contributed to:

2014

2012

2011

2010

2009

2007

2006

2005

2004

2003

2002

2001

2000

1999

1998

1997

Wrote 24 papers:

DAC-2014-EldibWTS #named #source code: QMS: Evaluating the Side-Channel Resistance of Masked Software from Source Code (HE, CW, MMIT, PS), p. 6.
DATE-2014-GhalatyAS #analysis #fault: Analyzing and eliminating the causes of fault sensitivity analysis (NFG, AA, PS), pp. 1–6.
TACAS-2014-EldibWS #smt #verification: SMT-Based Verification of Software Countermeasures against Side-Channel Attacks (HE, CW, PS), pp. 62–77.
DATE-2012-GuoSHGHNS #implementation: ASIC implementations of five SHA-3 finalists (XG, MS, SH, DG, MBH, LN, PS), pp. 1006–1011.
DATE-2011-ChenGSS #analysis #performance: Data-oriented performance analysis of SHA-3 candidates on FPGA accelerated computers (ZC, XG, AS, PS), pp. 1650–1655.
DATE-2010-ChenS #implementation #manycore #named #parallel #scalability: pSHS: A scalable parallel software implementation of Montgomery multiplication for multicore systems (ZC, PS), pp. 843–848.
DATE-2009-GuoS #bound #design #distributed #optimisation #using: Optimizing the HW/SW boundary of an ECC SoC design using control hierarchy and distributed storage (XG, PS), pp. 454–459.
DATE-2007-VerbauwhedeS #design #security #trust: Design methods for security and trust (IV, PS), pp. 672–677.
DATE-2006-SchaumontSV #design #hardware #semantics: Design with race-free hardware semantics (PS, SKS, IV), pp. 571–576.
DAC-2005-SchaumontLQV #architecture #design #energy #multi #thread: Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design (PS, BCCL, WQ, IV), pp. 27–30.
DAC-2005-TiriHHLYSV #embedded #encryption: A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing (KT, DDH, AH, BCL, SY, PS, IV), pp. 222–227.
DATE-2005-VillaSVMP #framework #integration #memory management #multi #performance: Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip (OV, PS, IV, MM, GP), pp. 804–805.
DATE-v1-2004-SchaumontV #interactive #partial evaluation: Interactive Cosimulation with Partial Evaluation (PS, IV), pp. 642–647.
DATE-v2-2004-VerbauwhedeSPK #architecture #design #embedded #energy #multi #performance: Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing (IV, PS, CP, BK), pp. 988–995.
DAC-2003-HwangLSSFYHV #design #embedded: Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system (DDH, BCL, PS, KS, YF, SY, AH, IV), pp. 60–65.
DAC-2002-SchaumontKV #design: Unlocking the design secrets of a 2.29 Gb/s Rijndael processor (PS, HK, IV), pp. 634–639.
DATE-2002-PaskoVS #c++ #design: Techniques to Evolve a C++ Based System Design Language (RP, SV, PS), pp. 302–309.
DAC-2001-SchaumontVKS #configuration management: A Quick Safari Through the Reconfiguration Jungle (PS, IV, KK, MS), pp. 172–177.
DATE-2000-LennardSJHH #design #question #standard: Standards for System-Level Design: Practical Reality or Solution in Search of a Question? (CKL, PS, GGdJ, AH, PH), pp. 576–583.
DAC-1999-SchaumontCVE #automation: A 10 Mbit/s Upstream Cable Modem with Automatic equalization (PS, RC, SV, ME), pp. 337–340.
DAC-1999-SchaumontCVEB #behaviour #hardware #reuse: Hardware Reuse at the Behavioral Level (PS, RC, SV, ME, IB), pp. 784–789.
DATE-1999-CmarRSVB #design #fixpoint #refinement: A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement (RC, LR, PS, SV, IB), p. 271–?.
DAC-1998-SchaumontVREB #design #programming: A Programming Environment for the Design of Complex High Speed ASICs (PS, SV, LR, ME, IB), pp. 315–320.
EDTC-1997-SchaumontVREB #multi #synthesis: Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications (PS, SV, LR, ME, IB), pp. 542–546.