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Travelled to:
1 × Germany
7 × USA
Collaborated with:
K.A.Sakallah M.R.Guthaus P.N.Parakh E.D.Marsman R.M.Senger K.L.Kraver D.Sylvester M.S.McCorquodale F.H.Gebara M.Upton T.Huff T.N.Mudge A.Chandna C.D.Kibler M.Roberts R.A.Ravindran P.D.Nagarkar G.S.Dasika S.A.Mahlke A.J.Drake T.D.Basso S.M.Gold C.R.Gauthier P.S.Stetson
Talks about:
clock (3) microsystem (2) placement (2) compil (2) power (2) microprocessor (1) methodolog (1) sequenti (1) instruct (1) challeng (1)

Person: Richard B. Brown

DBLP DBLP: Brown:Richard_B=

Contributed to:

DAC 20062006
CGO 20052005
DAC 20032003
DATE 20032003
DAC 20002000
DAC 19981998
DAC 19951995
ASPLOS 19941994

Wrote 8 papers:

DAC-2006-GuthausSB #programming #using
Clock buffer and wire sizing using sequential programming (MRG, DS, RBB), pp. 1041–1046.
CGO-2005-RavindranNDMSMB #compilation #power management
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache (RAR, PDN, GSD, EDM, RMS, SAM, RBB), pp. 179–190.
A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference (RMS, EDM, MSM, FHG, KLK, MRG, RBB), pp. 520–525.
DATE-2003-McCorquodaleGKMSB #challenge #design #top-down
A Top-Down Microsystems Design Methodology and Associated Challenges (MSM, FHG, KLK, EDM, RMS, RBB), pp. 20292–20296.
CGaAs PowerPC FXU (AJD, TDB, SMG, KLK, PNP, CRG, PSS, RBB), pp. 730–735.
DAC-1998-ParakhBS #polynomial
Congestion Driven Quadratic Placement (PNP, RBB, KAS), pp. 275–278.
DAC-1995-ChandnaKBRS #compilation #ram
The Aurora RAM Compiler (AC, CDK, RBB, MR, KAS), pp. 261–266.
ASPLOS-1994-UptonHMB #resource management
Resource Allocation in a High Clock Rate Microprocessor (MU, TH, TNM, RBB), pp. 98–109.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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