Travelled to:3 × USA
Collaborated with:S.K.Lim T.Song D.Petranovic C.Liu M.Jung Y.Wan B.W.Ku Y.Park K.Park S.Jang J.Choi
Talks about:optim (3) tsv (3) extract (2) power (2) coupl (2) full (2) chip (2) architectur (1) perspect (1) multipl (1)
Person: Yarui Peng
DBLP: Peng:Yarui
Contributed to:
201520142013Wrote 4 papers:
- DAC-2015-PengKPPJCL #3d #architecture #design #policy
- Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM (YP, BWK, YSP, KIP, SJJ, JSC, SKL), p. 6.
- DAC-2014-JungSWPL #3d #on the #perspective
- On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective (MJ, TS, YW, YP, SKL), p. 6.
- DAC-2014-PengPL #optimisation #performance
- Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling (YP, DP, SKL), p. 6.
- DAC-2013-SongLPL #3d #multi #optimisation
- Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs (TS, CL, YP, SKL), p. 7.