Stem tsv$ (all stems)

28 papers:

DATE-2015-LeeCSP #3d

A TSV noise-aware 3-D placer (YML, CC, JS, KTP), pp. 1653–1658.

DATE-2015-LoCH #architecture #clustering #fault

Architecture of ring-based redundant TSV for clustered faults (WHL, KC, TH), pp. 848–853.

DAC-2014-PengPL #optimisation #performance

Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling (YP, DP, SKL), p. 6.

DATE-2014-ChenLLSHC #3d

Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits (YGC, KYL, MCL, YS, WKH, SCC), pp. 1–4.

DATE-2014-WangFOT #3d #reduction

P/G TSV planning for IR-drop reduction in 3D-ICs (SW, FF, FO, MBT), pp. 1–6.

DAC-2013-DevWR #3d #integration #testing #using

High-throughput TSV testing and characterization for 3D integration using thermal mapping (KD, GW, SR), p. 6.

DAC-2013-JiangYXCE #3d #effectiveness #on the #performance

On effective and efficient in-field TSV repair for stacked 3D ICs (LJ, FY, QX, KC, BE), p. 6.

DAC-2013-LiP #framework #modelling

An accurate semi-analytical framework for full-chip TSV-induced stress modeling (YL, DZP), p. 8.

DAC-2013-SongLPL #3d #multi #optimisation

Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs (TS, CL, YP, SKL), p. 7.

DATE-2013-DeutschC #multi #using

Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels (SD, KC), pp. 1065–1070.

DATE-2013-LefterVTEHC #3d #integration #memory management #question

Is TSV-based 3D integration suitable for inter-die memory repair? (ML, GRV, MT, ME, SH, SDC), pp. 1251–1254.

DATE-2013-ShihW #3d #fault

An enhanced double-TSV scheme for defect tolerance in 3D-IC (HCS, CWW), pp. 1486–1489.

DAC-2012-JungPL #3d #reliability

Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs (MJ, DZP, SKL), pp. 317–326.

DAC-2012-YeC #3d #fault

TSV open defects in 3D integrated circuits: characterization, test, and optimal spare allocation (FY, KC), pp. 1024–1030.

DATE-2012-JiangXE #3d #effectiveness #on the

On effective TSV repair for 3D-stacked ICs (LJ, QX, BE), pp. 793–798.

DATE-2012-Marinissen #2d #3d #challenge #testing

Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs (EJM), pp. 1277–1282.

DATE-2012-XhakoniBG #3d #image #performance

Impact of TSV area on the dynamic range and frame rate performance of 3D-integrated image sensors (AX, DSSB, GGEG), pp. 836–839.

DATE-2012-XuYCJW #3d #performance

Efficient variation-aware EM-semiconductor coupled solver for the TSV structures in 3D IC (YX, WY, QC, LJ, NW), pp. 1409–1412.

DAC-2011-HsuCB #3d #design

TSV-aware analytical placement for 3D IC designs (MKH, YWC, VB), pp. 664–669.

DAC-2011-JungMPL #3d #analysis #optimisation #reliability

TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC (MJ, JM, DZP, SKL), pp. 188–193.

DAC-2011-LiuSCKKL #3d #analysis #optimisation

Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC (CL, TS, JC, JK, JK, SKL), pp. 783–788.

DAC-2011-LiuZYZ #3d #algorithm

An integrated algorithm for 3D-IC TSV assignment (XL, YZ, GKY, XZ), pp. 652–657.

DATE-2011-HealyL #3d #network #novel

A novel TSV topology for many-tier 3D power-delivery networks (MBH, SKL), pp. 261–264.

DAC-2010-YangALLP #3d #analysis #layout #optimisation

TSV stress aware timing analysis with applications to 3D-IC layout optimization (JSY, KA, YJL, SKL, DZP), pp. 803–806.

DATE-2010-HsiehHCTTL #3d #architecture #design

TSV redundancy: Architecture and design issues in 3D IC (ACH, TH, MTC, MHT, CMT, HCL), pp. 166–171.

DATE-2010-Marinissen #3d #testing

Testing TSV-based three-dimensional stacked ICs (EJM), pp. 1689–1694.

DATE-2010-WeerasekeraGPT #3d #on the

On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits (RW, MG, DP, HT), pp. 1325–1328.

HPCA-2010-WooSLL #3d #architecture #memory management

An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth (DHW, NHS, DLL, HHSL), pp. 1–12.