Travelled to:1 × Brazil
1 × France
1 × India
2 × USA
Collaborated with:S.Ma L.Huang N.D.E.Jerger K.Dai L.Shen N.Xiao H.Lu M.Lai M.Wang N.Benoit F.Bodin L.Gao Y.Lü R.Gong W.Chen F.Liu C.Liu W.Shi J.Guo Z.Pang F.Chen
Talks about:multi (4) processor (3) architectur (2) algorithm (2) effici (2) design (2) chip (2) base (2) heterogen (1) dimension (1)
Person: Zhiying Wang
DBLP: Wang:Zhiying
Contributed to:
2012
20112010
2010
2008
2008Wrote 9 papers:
- HPCA-2012-MaJW #communication #performance
- Supporting efficient collective communication in NoCs (SM, NDEJ, ZW), pp. 165–176.
- HPCA-2012-MaJW12a #adaptation #algorithm #design #performance
- Whole packet forwarding: Efficient design of fully adaptive routing algorithms for networks-on-chip (SM, NDEJ, ZW), pp. 467–478.
- DATE-2011-HuangWSLXL #embedded #low cost
- A specialized low-cost vectorized loop buffer for embedded processors (LH, ZW, LS, HL, NX, CL), pp. 1200–1203.
- HPCA-2010-HuangSWSXM #named #permutation
- SIF: Overcoming the limitations of SIMD devices via implicit permutation (LH, LS, ZW, WS, NX, SM), pp. 1–12.
- PDP-2010-WangBBW #approach #modelling #parallel #search-based #source code
- Model Driven Iterative Multi-dimensional Parallelization of Multi-task Programs for the Cell BE: A Genetic Algorithm-Based Approach (MW, NB, FB, ZW), pp. 218–222.
- DAC-2008-LaiWGLD #architecture
- A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers (McL, ZW, LG, HL, KD), pp. 630–633.
- DAC-2008-LuSHWX #effectiveness #multi #optimisation
- Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques (YSL, LS, LH, ZW, NX), pp. 197–200.
- SAC-2008-GuoLPHCDW #design #manycore #memory management
- Hierarchical memory system design for a heterogeneous multi-core processor (JG, McL, ZP, LH, FC, KD, ZW), pp. 1504–1508.
- SAC-2008-RuiWFKZ #architecture #control flow
- Control flow checking and recovering based on 8051 architecture (RG, WC, FL, KD, ZW), pp. 1550–1551.