BibSLEIGH — Avi

Travelled to:

11 × USA
2 × France
2 × Germany

Collaborated with:

∅ A.Nahir S.Fine S.Ur Y.Katz M.Rimon E.Marcus Y.Malka A.Adir V.Bertacco G.Shurek C.Meissner D.Chatterjee R.Morad S.Asaf S.Lan A.E.Gamal J.Schumann S.Landa A.Koyfman G.Shaked O.Lachish A.J.Hu R.Emek T.Keidar N.Ronen R.Grinwald E.Harel M.Orgad B.Mammo D.Pidan M.Golubev V.Sokhin S.Copty F.Bacchini T.Fitzpatrick R.Ranjan D.Lacey M.Tan A.Piziali R.Galivanche M.Abramovici A.Camilleri B.Bentley H.Foster S.Kapoor D.Goodman D.Hershcovich O.Hershkovitz B.G.Hickerson K.Holtz W.Kadry J.M.Ludden R.R.Pratt M.Schiffli B.S.Onge B.W.Thompto E.Tsanko

Talks about:

verif (9) silicon (7) coverag (7) function (5) generat (5) post (4) instruct (3) analysi (3) valid (3) pre (3)

Person: Avi Ziv

DBLP: Ziv:Avi

Contributed to:

2014

2012

2011

2010

2007

2006

2004

2003

2002

1998

1994

Wrote 20 papers:

DAC-2014-AdirGHHHHKKLMNPSOTTZ #memory management #transaction #verification: Verification of Transactional Memory in POWER8 (AA, DG, DH, OH, BGH, KH, WK, AK, JML, CM, AN, RRP, MS, BSO, BWT, ET, AZ), p. 6.
DAC-2012-ChatterjeeKMZB #architecture #platform: Checking architectural outputs instruction-by-instruction on acceleration platforms (DC, AK, RM, AZ, VB), pp. 955–961.
DATE-2012-KatzRZ #csp #generative #using: Generating instruction streams using abstract CSP (YK, MR, AZ), pp. 15–20.
DATE-2012-MammoCPNZMB #approximate #simulation: Approximating checkers for simulation acceleration (BM, DC, DP, AN, AZ, RM, VB), pp. 153–158.
DAC-2011-AdirGLNSSZ #concurrent #multi #named #thread: Threadmill: a post-silicon exerciser for multi-threaded processors (AA, MG, SL, AN, GS, VS, AZ), pp. 860–865.
DAC-2011-AdirNSZMS #validation #verification: Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor (AA, AN, GS, AZ, CM, JS), pp. 569–574.
DAC-2011-KatzRZS #architecture #behaviour #generative #learning #quality: Learning microarchitectural behaviors to improve stimuli generation quality (YK, MR, AZ, GS), pp. 848–853.
DATE-2011-AdirCLNSZMS #validation #verification: A unified methodology for pre-silicon verification and post-silicon validation (AA, SC, SL, AN, GS, AZ, CM, JS), pp. 1590–1595.
DAC-2010-NahirZGHACBFBK #validation #verification: Bridging pre-silicon verification and post-silicon validation (AN, AZ, RG, AJH, MA, AC, BB, HF, VB, SK), pp. 94–95.
DAC-2007-BacchiniHFRLTPZ #question #verification: Verification Coverage: When is Enough, Enough? (FB, AJH, TF, RR, DL, MT, AP, AZ), pp. 744–745.
DAC-2006-NahirZEKR #generative #multi #testing #verification: Scheduling-based test-case generation for verification of multimedia SoCs (AN, AZ, RE, TK, NR), pp. 348–351.
DAC-2004-AsafMZ #analysis #functional: Defining coverage views to improve functional coverage analysis (SA, EM, AZ), pp. 41–44.
DAC-2004-FineUZ #functional #probability #verification: Probabilistic regression suites for functional verification (SF, SU, AZ), pp. 49–54.
DATE-v1-2004-Ziv #generative: Stimuli Generation with Late Binding of Values (AZ), pp. 558–563.
DAC-2003-FineZ #functional #generative #network #testing #using #verification: Coverage directed test generation for functional verification using bayesian networks (SF, AZ), pp. 286–291.
DATE-2003-Ziv #functional #metric: Cross-Product Functional Coverage Measurement with Temporal Properties-Based Assertions (AZ), pp. 10834–10841.
DAC-2002-LachishMUZ #analysis #functional: Hole analysis for functional coverage data (OL, EM, SU, AZ), pp. 807–812.
DAC-1998-GrinwaldHOUZ #design #tool support #verification: User Defined Coverage — A Tool Supported Methodology for Design Verification (RG, EH, MO, SU, AZ), pp. 158–163.
DAC-1998-MalkaZ #analysis #debugging #design #estimation #reliability #statistics: Design Reliability — Estimation through Statistical Analysis of Bug Discovery Data (YM, AZ), pp. 644–649.
DAC-1994-LanZG #multi #programmable: Placement and Routing for a Field Programmable Multi-Chip Module (SL, AZ, AEG), pp. 295–300.