Travelled to:1 × Germany
2 × USA
3 × France
Collaborated with:J.E.Chen W.C.Wu J.Zha X.Cui J.Lin M.C.Lin W.Y.Lin T.Hwang W.Shen C.P.Wu C.Su Y.Chen M.Huang G.Chen
Talks about:fault (5) circuit (3) simul (3) delay (3) pattern (2) memori (2) measur (2) effici (2) test (2) probabilist (1)
Person: Chung-Len Lee
DBLP: Lee:Chung=Len
Contributed to:
2012200220001994
19911990Wrote 7 papers:
- DATE-2012-ZhaCL #fault #memory management #modelling #testing
- Modeling and testing of interference faults in the nano NAND Flash memory (JZ, XC, CLL), pp. 527–531.
- DATE-2002-LinLC #feedback #performance
- An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits (JWL, CLL, JEC), p. 1119.
- DATE-2000-SuCHCL #metric
- All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses (CS, YTC, MJH, GNC, CLL), pp. 527–531.
- EDAC-1994-LinCL #fault #named #performance
- TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator (MCL, JEC, CLL), pp. 508–512.
- EDAC-1994-WuLCL #clustering #distributed #fault #simulation
- Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning (WCW, CLL, JEC, WYL), p. 661.
- DAC-1991-WuL #fault #probability #testing
- A Probabilistic Testability Measure for Delay Faults (WCW, CLL), pp. 440–445.
- DAC-1990-HwangLSW #fault #parallel
- A Parallel Pattern Mixed-Level Fault Simulator (TSH, CLL, WZS, CPW), pp. 716–719.