BibSLEIGH — Sung-Mo

Travelled to:

1 × France
1 × Germany
11 × USA

Collaborated with:

K.Kim A.Dharchoudhury S.Jung C.Teng C.Tsai T.Li E.Rosenbaum J.Kim M.Sriram Y.Shih C.L.Liu Y.Cheng J.Lee U.Narayanan L.Yuan R.H.Krambeck H.S.Law T.Hwang P.Saxena

Talks about:

logic (6) circuit (5) cmos (5) dual (4) threshold (3) synthesi (3) voltag (3) layout (3) domino (3) design (3)

Person: Sung-Mo Kang

DBLP: Kang:Sung=Mo

Contributed to:

2002

2001

2000

1999

1998

1997

1996

1993

1992

1991

1982

Wrote 18 papers:

DAC-2002-JungKK #logic: Low-swing clock domino logic incorporating dual supply and dual threshold voltages (SOJ, KWK, SMK), pp. 467–472.
DAC-2002-LeeKK #named #verification: VeriCDF: a new verification methodology for charged device failures (JL, KWK, SMK), pp. 874–879.
DATE-2002-JungKK #logic #performance #synthesis: Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain (SOJ, KWK, SMK), pp. 260–265.
DAC-2001-KimJSLK #optimisation #using: Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique (KWK, SOJ, PS, CLL, SMK), pp. 732–737.
DAC-2000-KimNK #logic #synthesis: Domino logic synthesis minimizing crosstalk (KWK, UN, SMK), pp. 280–285.
DAC-2000-TsaiK #performance #reduction #simulation: Fast temperature calculation for transient electrothermal simulation by mixed frequency/time domain thermal model reduction (CHT, SMK), pp. 750–755.
DAC-1999-LiTRK #modelling #simulation: Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation (TL, CHT, ER, SMK), pp. 549–554.
DATE-1999-KimKHL #logic #power management #synthesis: Logic Transformation for Low Power Synthesis (KWK, SMK, TH, CLL), pp. 158–162.
DAC-1998-LiK #layout #verification: Layout Extraction and Verification Methodology CMOS I/O Circuits (TL, SMK), pp. 291–296.
DAC-1997-KimK #algorithm #design #layout #performance: An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design (JK, SMK), pp. 456–459.
DAC-1997-YuanTK #estimation #statistics: Statistical Estimation of Average Power Dissipation in Sequential Circuits (LPY, CCT, SMK), pp. 377–382.
DAC-1996-ChengTDRK #named #reliability: iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips (YKC, CCT, AD, ER, SMK), pp. 548–551.
DAC-1996-TengCRK #reliability: Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects (CCT, YKC, ER, SMK), pp. 752–757.
DAC-1993-DharchoudhuryK #variability #worst-case: Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits (AD, SMK), pp. 154–158.
DAC-1993-SriramK #approximate #performance: Fast Approximation of the Transient Response of Lossy Transmision Line Trees (MS, SMK), pp. 691–696.
DAC-1992-DharchoudhuryK #approach #design #optimisation #worst-case: An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits (AD, SMK), pp. 704–709.
DAC-1991-ShihK #approach #equation #named #performance #using: ILLIADS: A New Fast MOS Timing Simulator Using Direct Equation-Solving Approach (YHS, SMK), pp. 20–25.
DAC-1982-KangKL #adaptation #cpu #design #evolution #layout #logic #matrix #random: Gate matrix layout of random control logic in a 32-bit CMOS CPU chip adaptable to evolving logic design (SMK, RHK, HFSL), pp. 170–174.