Stem die$ (all stems)

36 papers:

SANER-2015-AmmerlaanVZ #refactoring #why

Old habits die hard: Why refactoring for understandability does not give immediate benefits (EA, WV, AZ), pp. 504–507.

HPCA-2015-MeswaniBRSIL #approach #architecture #memory management

Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories (MRM, SB, DR, JS, MI, GHL), pp. 126–136.

DAC-2014-ChienHLYC #testing

Contactless Stacked-die Testing for Pre-bond Interposers (JHC, RSH, HJL, KYY, SCC), p. 6.

DAC-2014-GuinZFT #low cost

Low-cost On-Chip Structures for Combating Die and IC Recycling (UG, XZ, DF, MT), p. 6.

DAC-2014-KimM #3d #design #on the #reliability

On the Design of Reliable 3D-ICs Considering Charged Device Model ESD Events During Die Stacking (DK, SM), p. 6.

DATE-2014-ChenTCC #effectiveness

Cost-effective decap selection for beyond die power integrity (YEC, THT, SHC, HMC), pp. 1–4.

SCSM-2014-FrischlichRR #identification #social

I’d Rather Die Than Be with You: The Effects of Mortality Salience and Negative Social Identity on Identification with a Virtual Group (LF, DR, OR), pp. 440–451.

DATE-2013-El-NacouziAPZJM #detection #scalability

A dual grain hit-miss detector for large die-stacked DRAM caches (MEN, IA, MP, JZ, NDEJ, AM), pp. 89–92.

DATE-2013-LefterVTEHC #3d #integration #memory management #question

Is TSV-based 3D integration suitable for inter-die memory repair? (ML, GRV, MT, ME, SH, SDC), pp. 1251–1254.

DAC-2012-AthikulwongsePL #3d

Exploiting die-to-die thermal coupling in 3D IC placement (KA, MP, SKL), pp. 741–746.

DATE-2012-ChenLMABJ #3d #architecture #in memory #memory management #modelling #named

CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory (KC, SL, NM, JHA, JBB, NPJ), pp. 33–38.

DAC-2011-AarestadLPAA #process

Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect (JA, CL, JP, DA, KA), pp. 534–539.

DATE-2011-ButtrickK #3d #network #on the #testing #using

On testing prebond dies with incomplete clock networks in a 3D IC using DLLs (MB, SK), pp. 1418–1423.

DATE-2011-KimYLAJ #3d #analysis #embedded #mobile #performance

A quantitative analysis of performance benefits of 3D die stacking on mobile and embedded SoC (DK, SY, SL, JHA, HJ), pp. 1333–1338.

DAC-2010-BansalRYJLMMR #3d #question

3-D stacked die: now or future? (SB, JCR, AY, MSJ, LCL, PM, PM, RR), pp. 298–299.

DAC-2010-Chiprout #power management

On-die power grids: the missing link (EC), pp. 940–945.

DATE-2010-PascaARLC #3d #communication #fault

Error resilience of intra-die and inter-die communication with 3D spidergon STNoC (VP, LA, CR, RL, MC), pp. 275–278.

DAC-2009-ChengGSQH #modelling #variability

Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability (LC, PG, CJS, KQ, LH), pp. 104–109.

DAC-2009-VeetilSBSR #analysis #dependence #performance

Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence (VV, DS, DB, SS, SR), pp. 154–159.

DHM-2009-JeonJKH #classification #gender #using

Facial Gender Classification Using LUT-Based Sub-images and DIE (JBJ, SHJ, DJK, KSH), pp. 36–45.

DATE-2008-SingheeSR #correlation #kernel #performance #statistics

Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing (AS, SS, RAR), pp. 856–861.

CHI-2008-Grammenos #game studies #learning

Game over: learning by dying (DG), pp. 1443–1452.

DAC-2007-HeloueAN #correlation #estimation #modelling

Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation (KRH, NA, FNN), pp. 93–98.

DATE-2007-ZjajoAG #interactive #monitoring #parametricity #process

Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits (AZ, MJBA, JPdG), pp. 1301–1306.

DAC-2006-BhardwajVGC #analysis #modelling #optimisation #process

Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits (SB, SBKV, PG, YC), pp. 791–796.

DAC-2006-GhantaVBP #analysis #correlation #power management #probability #scalability

Stochastic variational analysis of large power grids considering intra-die correlations (PG, SBKV, SB, RP), pp. 211–216.

DAC-2006-LuoSSKC

An IC manufacturing yield model considering intra-die variations (JL, SS, QS, JK, CC), pp. 749–754.

PLDI-2006-BergerZ #memory management #named #probability #safety

DieHard: probabilistic memory safety for unsafe languages (EDB, BGZ), pp. 158–168.

DATE-2005-MangassarianA #analysis #on the #statistics

On Statistical Timing Analysis with Inter- and Intra-Die Variations (HM, MA), pp. 132–137.

DATE-v1-2004-ChenG #adaptation #bias #low cost #performance #power management #reduction

A Low Cost Individual-Well Adaptive Body Bias (IWABB) Scheme for Leakage Power Reduction and Performance Enhancement in the Presence of Intra-Die Variations (TWC, JG), pp. 240–245.

DAC-2003-FerzliN #estimation #grid #power management #process #statistics

Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations (IAF, FNN), pp. 856–859.

PADL-2003-Mogensen #specification

Roll : A Language for Specifying Die-Rolls (TÆM), pp. 145–159.

DAC-2000-MehrotraSBCVN #modelling #performance

A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance (VM, SLS, DSB, AC, RV, SRN), pp. 172–175.

TACAS-1998-BrockmeyerW #design #verification

Tamagotchis Need Not Die — Verification of STATEMENT Design (UB, GW), pp. 217–231.

CHI-1996-WagnerC #user interface

Demo or Die: User Interface as Marketing Theatre (AW, MC), pp. 458–465.

DAC-1982-InoueAF #design #layout #precise

A layout system for high precision design of progressive die (KI, MA, TF), pp. 246–252.