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Travelled to:
1 × China
1 × India
7 × USA
Collaborated with:
N.Muralimanohar A.Shafiee K.Sudan A.Davis M.Taassori M.Awasthi A.N.Udipi N.Chatterjee J.B.Carter K.Ramani V.Venkatachalapathy Chandrasekhar Nagarajan M.Tiwari N.Madan L.Zhao R.Iyer S.Makineni D.Newell N.P.Jouppi M.Shevgoor B.Rajendran V.Srinivasan D.W.Nellans G.Semeraro G.Magklis D.H.Albonesi S.Dwarkadas M.L.Scott C.Xu D.Niu T.Zhang S.Yu Y.Xie S.Balakrishnan S.Lie M.Xu D.Mallick G.Lauterbach S.H.Pugsley Z.Chishti C.Wilkerson P.Chuang R.L.Scott A.Jaleel S.Lu K.Chow X.Jiang M.Upton Y.Solihin
Talks about:
effici (5) dram (4) architectur (3) memori (3) page (3) cach (3) placement (2) prefetch (2) energi (2) scale (2)

Person: Rajeev Balasubramonian

DBLP DBLP: Balasubramonian:Rajeev

Facilitated 1 volumes:


Contributed to:

HPCA 20152015
HPCA 20142014
HPCA 20132013
HPCA 20122012
ASPLOS 20102010
HPCA 20102010
HPCA 20092009
HPCA 20052005
HPCA 20022002
ASPLOS 20182018
ASPLOS 20192019

Wrote 15 papers:

HPCA-2015-XuNMBZY0 #architecture #challenge #memory management
Overcoming the challenges of crossbar resistive memory architectures (CX, DN, NM, RB, TZ, SY, YX), pp. 476–488.
HPCA-2014-PugsleyCWCSJLCB #evaluation #runtime
Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers (SHP, ZC, CW, PfC, RLS, AJ, SLL, KC, RB), pp. 626–637.
HPCA-2014-ShafieeTBD #memory management #named
MemZip: Exploring unconventional benefits from memory compression (AS, MT, RB, AD), pp. 638–649.
HPCA-2013-SudanBLXMLB #architecture #lightweight #novel #using #web
A novel system architecture for web scale applications using lightweight CPUs and virtualized I/O (KS, SB, SL, MX, DM, GL, RB), pp. 167–178.
HPCA-2012-AwasthiSSRBS #performance
Efficient scrub mechanisms for error-prone emerging memories (MA, MS, KS, BR, RB, VS), pp. 15–26.
HPCA-2012-ChatterjeeMBDJ #staged
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads (NC, NM, RB, AD, NPJ), pp. 41–52.
ASPLOS-2010-SudanCNABD #named #performance
Micro-pages: increasing DRAM efficiency with locality-aware data placement (KS, NC, DWN, MA, RB, AD), pp. 219–230.
HPCA-2010-JiangMZUIMNSB #adaptation #named
CHOP: Adaptive filter-based DRAM caching for CMP server platforms (XJ, NM, LZ, MU, RI, SM, DN, YS, RB), pp. 1–12.
HPCA-2010-UdipiMB #energy #network #scalability #towards
Towards scalable, energy-efficient, bus-based on-chip networks (ANU, NM, RB), pp. 1–12.
HPCA-2009-AwasthiSBC #capacity #scalability
Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches (MA, KS, RB, JBC), pp. 250–261.
HPCA-2009-MadanZMUBIMN #3d #capacity #communication #configuration management #optimisation
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy (NM, LZ, NM, ANU, RB, RI, SM, DN), pp. 262–274.
HPCA-2005-BalasubramonianMRV #architecture #performance
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures (RB, NM, KR, VV), pp. 28–39.
HPCA-2002-SemeraroMBADS #design #energy #multi #scalability #using
Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling (GS, GM, RB, DHA, SD, MLS), pp. 29–42.
ASPLOS-2018-TaassoriSB #named #performance #verification
VAULT: Reducing Paging Overheads in SGX with Efficient Integrity Verification Structures (MT, AS, RB), pp. 665–678.
ASPLOS-2019-NagarajanSBT #named
ρ: Relaxed Hierarchical ORAM (CN, AS, RB, MT), pp. 659–671.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.