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Travelled to:
1 × USA
2 × Germany
5 × France
Collaborated with:
V.Chandra S.Idgunji B.H.Calhoun M.R.Choudhury K.Mohanram F.Muradali C.Pietrzyk A.Domic J.Boley L.Lai P.Gupta S.Nalam A.J.Strojwas E.Macii M.Pedram D.Friebel R.Zafalon M.Wieckowski D.Sylvester D.Blaauw N.Ns J.C.Rey J.Kawa C.Lütkemeyer V.Pitchumani S.Trimberger M.Casale-Rossi C.Guardiani P.Magarshack D.Pattullo J.Sawicki
Talks about:
sram (7) write (4) nanoscal (3) voltag (3) design (3) dynam (3) time (3) low (3) methodolog (2) analysi (2)

Person: Robert C. Aitken

DBLP DBLP: Aitken:Robert_C=

Contributed to:

DATE 20132013
DATE 20112011
DAC 20102010
DATE 20102010
DATE 20092009
DATE 20072007
DATE 20062006
DATE DF 20042004

Wrote 14 papers:

DATE-2013-BoleyCAC #analysis #estimation #performance
Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write VMIN (JB, VC, RCA, BHC), pp. 1819–1824.
DATE-2013-LaiCAG #monitoring #named #online
SlackProbe: a low overhead in situ on-line timing slack monitoring methodology (LL, VC, RCA, PG), pp. 282–287.
Analytical model for SRAM dynamic write-ability degradation due to gate oxide breakdown (VC, RCA), pp. 1172–1175.
Dynamic write limited minimum operating voltage for nanoscale SRAMs (SN, VC, RCA, BHC), pp. 467–472.
DAC-2010-NSRKALPST #problem #question #variability
Who solves the variability problem? (NN, JCR, JK, RCA, CL, VP, AJS, ST), pp. 218–219.
DATE-2010-ChandraPA #on the
On the efficacy of write-assist techniques in low voltage nanoscale SRAMs (VC, CP, RCA), pp. 345–350.
DATE-2010-ChoudhuryCMA #logic #performance
Analytical model for TDDB-based performance degradation in combinational logic (MRC, VC, KM, RCA), pp. 423–428.
DATE-2010-ChoudhuryCMA10a #fault #named #online
TIMBER: Time borrowing and error relaying for online timing error resilience (MRC, VC, KM, RCA), pp. 1554–1559.
DATE-2010-WieckowskiSBCIPA #analysis #black box
A black box method for stability analysis of arbitrary SRAM cell structures (MW, DS, DB, VC, SI, CP, RCA), pp. 795–800.
DATE-2009-ChandraA #reliability #scalability
Impact of voltage scaling on nanoscale SRAM reliability (VC, RCA), pp. 387–392.
DATE-2007-AitkenI #design #embedded #worst-case
Worst-case design and margin for embedded SRAM (RCA, SI), pp. 1289–1294.
DATE-2007-Casale-RossiSADGMPS #named #product line #question #trust
DFM/DFY: should you trust the surgeon or the family doctor? (MCR, AJS, RCA, AD, CG, PM, DP, JS), pp. 439–442.
DATE-2006-MaciiPFADZ #design #matter #power management #question #tool support
Low-power design tools: are EDA vendors taking this matter seriously? (EM, MP, DF, RCA, AD, RZ), p. 1227.
DATE-DF-2004-AitkenM #dependence #design
From Working Design Flow to Working Chips: Dependencies and Impacts of Methodology Decisions (RCA, FM), p. 2.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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