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Travelled to:
3 × USA
Collaborated with:
L.T.Pileggi F.Dartu R.Gupta B.Krauter J.Willis A.Dharchoudhury R.Panda D.Blaauw R.Vaidyanathan D.Bearden
Talks about:
power (2) delay (2) microprocessor (1) interconnect (1) macromodel (1) distribut (1) explicit (1) approxim (1) respons (1) network (1)

Person: Bogdan Tutuianu

DBLP DBLP: Tutuianu:Bogdan

Contributed to:

DAC 19981998
DAC 19961996
DAC 19951995

Wrote 4 papers:

DAC-1998-DharchoudhuryPBVTB #analysis #design #network
Design and Analysis of Power Distribution Networks in PowerPC Microprocessors (AD, RP, DB, RV, BT, DB), pp. 738–743.
DAC-1996-DartuTP #megamodelling #simulation
RC-Interconnect Macromodels for Timing Simulation (FD, BT, LTP), pp. 544–547.
DAC-1996-TutuianuDP #approximate
An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response (BT, FD, LTP), pp. 611–616.
DAC-1995-GuptaKTWP #bound
The Elmore Delay as a Bound for RC Trees with Generalized Input Signals (RG, BK, BT, JW, LTP), pp. 364–369.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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