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Travelled to:
1 × Italy
2 × Germany
3 × France
3 × USA
Collaborated with:
R.Drechsler J.Malburg A.Finder A.Sülflow M.Dehbashi H.Riener S.Frehse D.Große S.Safarpour A.G.Veneris K.Winkelmann H.Trylus D.Stoffel R.Aitken Z.T.Kalbarczyk F.Reichenbach M.S.Reorda C.Braunstein U.Kühne F.Rogin T.Klotz S.Rülke
Talks about:
base (5) hardwar (3) analysi (3) design (3) understand (2) generat (2) automat (2) formal (2) verif (2) toler (2)

Person: Görschwin Fey

DBLP DBLP: Fey:G=ouml=rschwin

Contributed to:

PDP 20142014
DATE 20132013
DAC 20122012
DAC 20112011
DAC 20092009
DATE 20092009
DATE 20082008
DATE 20062006
SFM 20062006
DATE v1 20042004

Wrote 13 papers:

PDP-2014-DehbashiF #debugging #multi #online #transaction
Transaction-Based Online Debug for NoC-Based Multiprocessor SoCs (MD, GF), pp. 400–404.
DATE-2013-AitkenFKRR #analysis #how #question #reliability
Reliability analysis reloaded: how will we survive? (RA, GF, ZTK, FR, MSR), pp. 358–367.
DATE-2013-MalburgFF #analysis #comprehension #data flow #design
Tuning dynamic data flow analysis to support design understanding (JM, AF, GF), pp. 1179–1184.
DATE-2013-RienerFF #fault tolerance
Improving fault tolerance utilizing hardware-software-co-synthesis (HR, SF, GF), pp. 939–942.
DAC-2012-MalburgFF #automation #design #hardware #locality #metric #using
Automated feature localization for hardware designs using coverage metrics (JM, AF, GF), pp. 941–946.
DAC-2011-Fey #analysis #data flow #multi
Orchestrated multi-level information flow analysis to understand SoCs (GF), pp. 284–285.
DAC-2009-FeySD #bound #fault tolerance #using
Computing bounds for fault tolerance using formal techniques (GF, AS, RD), pp. 190–195.
DATE-2009-SulflowFBKD #debugging #satisfiability
Increasing the accuracy of SAT-based debugging (AS, GF, CB, UK, RD), pp. 1326–1331.
DATE-2008-RoginKFDR #automation #design #generative #hardware
Automatic Generation of Complex Properties for Hardware Designs (FR, TK, GF, RD, SR), pp. 545–548.
DATE-2006-FeyGD #verification
Avoiding false negatives in formal verification for protocol-driven blocks (GF, DG, RD), pp. 1225–1226.
DATE-2006-FeySVD #on the #satisfiability
On the relation between simulation-based and SAT-based diagnosis (GF, SS, AGV, RD), pp. 1139–1144.
SFM-2006-DrechslerF #automation #generative
Automatic Test Pattern Generation (RD, GF), pp. 30–55.
DATE-v1-2004-WinkelmannTSF #low cost #verification
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor (KW, HJT, DS, GF), pp. 162–167.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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