Travelled to:1 × France
3 × Germany
3 × USA
Collaborated with:R.Drechsler D.Große V.Herdt R.Wille G.W.Dueck M.Diepenbeck U.Kühne J.Seiter M.Soeken J.Oetjens N.Bannow M.Becker O.Bringmann A.Burger M.Chaari S.Chakraborty W.Ecker K.Grüttner T.Kruse C.Kuznik M.Mauderer W.Müller D.Müller-Gritschneder F.Poppen H.Post S.Reiter W.Rosenstiel S.Roth U.Schlichtmann A.v.Schwerin B.Tabacaru A.Viehl
Talks about:system (4) verifi (3) use (3) symbol (2) design (2) state (2) simul (2) intermedi (1) synthesi (1) research (1)
Person: Hoang M. Le
DBLP: Le:Hoang_M=
Contributed to:
20152014
201420132013
20122008Wrote 7 papers:
- DAC-2015-HerdtLD #simulation #using #verification
- Verifying SystemC using stateful symbolic simulation (VH, HML, RD), p. 6.
- DAC-2014-OetjensBBBBCCDEGKKLM0MPPRRRSSTV #challenge #evaluation #prototype #research #safety #state of the art #using
- Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges (JHO, NB, MB, OB, AB, MC, SC, RD, WE, KG, TK, CK, HML, MM, WM, DMG, FP, HP, SR, WR, SR, US, AvS, BAT, AV), p. 6.
- DATE-2014-LeD #design #towards #verification
- Towards verifying determinism of SystemC designs (HML, RD), pp. 1–4.
- DAC-2013-LeGHD #simulation #using #verification
- Verifying SystemC using an intermediate verification language and symbolic simulation (HML, DG, VH, RD), p. 6.
- DATE-2013-LeGD #design #fault #locality #scalability
- Scalable fault localization for SystemC TLM designs (HML, DG, RD), pp. 35–38.
- ICGT-2012-DrechslerDGKLSSW #development
- Completeness-Driven Development (RD, MD, DG, UK, HML, JS, MS, RW), pp. 38–50.
- DATE-2008-WilleLDG #logic #quantifier #synthesis
- Quantified Synthesis of Reversible Logic (RW, HML, GWD, DG), pp. 1015–1020.