Travelled to:1 × USA
2 × France
2 × Germany
Collaborated with:J.L.v.Meerbergen M.Ashouei J.Dielissen M.Quax B.Liu J.P.d.Gyvez A.Kumar A.Hansson H.Corporaal M.Cocco M.J.M.Heijligers A.Hekstra V.Sharma S.Cosemans F.Catthoor W.Dehaene M.Bekooij F.Harmsze S.Sawitzki A.v.d.Werf
Talks about:reconfigur (2) processor (2) scalabl (2) power (2) subthreshold (1) architectur (1) implement (1) circuitri (1) standard (1) interact (1)
Person: Jos Huisken
DBLP: Huisken:Jos
Contributed to:
2012
2012200720042001Wrote 6 papers:
- DAC-2012-LiuAHG #standard
- Standard cell sizing for subthreshold operation (BL, MA, JH, JPdG), pp. 962–967.
- DATE-2012-SharmaCAHCD #power management #variability
- Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM (VS, SC, MA, JH, FC, WD), pp. 1042–1047.
- DATE-2007-KumarHHC #configuration management #design #interactive #multi
- Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip (AK, AH, JH, HC), pp. 117–122.
- DATE-DF-2004-CoccoDHHH #architecture #scalability
- A Scalable Architecture for LDPC Decodin (MC, JD, MJMH, AH, JH), pp. 88–95.
- DATE-DF-2004-QuaxHM #configuration management #implementation #scalability
- A Scalable Implementation of a Reconfigurable WCDMA Rake Receiver (MQ, JH, JLvM), pp. 230–235.
- DATE-2001-DielissenMBHSHW #power management
- Power-efficient layered turbo decoder processor (JD, JLvM, MB, FH, SS, JH, AvdW), pp. 246–251.